From 2d9730cee599e889a7f05f3a703b9af8a7df0a70 Mon Sep 17 00:00:00 2001
From: Matthieu Cattin <matthieu.cattin@cern.ch>
Date: Fri, 31 Jan 2014 15:33:22 +0100
Subject: [PATCH] core: Add err, rty and int signals to the wishbone masters
interfaces. Terminate wb cycle in case of err on csr wb bus.
Note: The wb crossbar asserts err in case of access to un-mapped address.
Therefore to avoid host hang in case of access to un-mapped address,
the wb cycle is terminated (and returns 0xFFFFFFFF in case of read cycle).
---
hdl/gn4124core/rtl/spartan6/gn4124_core.vhd | 13 +++++++++++--
hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd | 13 +++++++++++--
hdl/gn4124core/rtl/wbmaster32.vhd | 16 +++++++++++++++-
3 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd b/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
index 68842ef..538f73e 100644
--- a/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
@@ -121,6 +121,9 @@ entity gn4124_core is
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
+ csr_err_i : in std_logic;
+ csr_rty_i : in std_logic; -- not used internally
+ csr_int_i : in std_logic; -- not used internally
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
@@ -133,7 +136,10 @@ entity gn4124_core is
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
- dma_stall_i : in std_logic
+ dma_stall_i : in std_logic;
+ dma_err_i : in std_logic; -- not used internally
+ dma_rty_i : in std_logic; -- not used internally
+ dma_int_i : in std_logic -- not used internally
);
end gn4124_core;
@@ -537,7 +543,10 @@ begin
wb_stb_o => csr_stb_o,
wb_we_o => csr_we_o,
wb_ack_i => csr_ack_i,
- wb_stall_i => csr_stall_i
+ wb_stall_i => csr_stall_i,
+ wb_err_i => csr_err_i,
+ wb_rty_i => csr_rty_i,
+ wb_int_i => csr_int_i
);
-- Adapt address bus width for top level
diff --git a/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd b/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
index 03235bd..aca65e2 100644
--- a/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
@@ -138,6 +138,9 @@ package gn4124_core_pkg is
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
+ csr_err_i : in std_logic;
+ csr_rty_i : in std_logic;
+ csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
@@ -150,7 +153,10 @@ package gn4124_core_pkg is
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
- dma_stall_i : in std_logic
+ dma_stall_i : in std_logic;
+ dma_err_i : in std_logic;
+ dma_rty_i : in std_logic;
+ dma_int_i : in std_logic
);
end component gn4124_core;
@@ -303,7 +309,10 @@ package gn4124_core_pkg is
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
- wb_stall_i : in std_logic -- Stall
+ wb_stall_i : in std_logic; -- Stall
+ wb_err_i : in std_logic; -- Error
+ wb_rty_i : in std_logic; -- Retry
+ wb_int_i : in std_logic -- Interrupt
);
end component; -- wbmaster32
diff --git a/hdl/gn4124core/rtl/wbmaster32.vhd b/hdl/gn4124core/rtl/wbmaster32.vhd
index 05a6b5a..ec27f8b 100644
--- a/hdl/gn4124core/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/rtl/wbmaster32.vhd
@@ -101,7 +101,10 @@ entity wbmaster32 is
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
- wb_stall_i : in std_logic -- Stall
+ wb_stall_i : in std_logic; -- Stall
+ wb_err_i : in std_logic; -- Error
+ wb_rty_i : in std_logic; -- Retry
+ wb_int_i : in std_logic -- Interrupt
);
end wbmaster32;
@@ -144,6 +147,7 @@ architecture behaviour of wbmaster32 is
signal wishbone_current_state : wishbone_state_type;
signal wb_ack_t : std_logic;
+ signal wb_err_t : std_logic;
signal wb_dat_i_t : std_logic_vector(31 downto 0);
signal wb_cyc_t : std_logic;
signal wb_dat_o_t : std_logic_vector(31 downto 0);
@@ -443,6 +447,15 @@ begin
-- end of the bus cycle
wb_cyc_t <= '0';
wishbone_current_state <= WB_IDLE;
+ elsif (wb_err_t = '1') then
+ -- e.g. when trying to access unmapped wishbone addresses, ERR is set
+ if (wb_we_t = '0') then
+ from_wb_fifo_din <= (others => '1'); -- dummy data as the transaction failed
+ from_wb_fifo_wr <= '1';
+ end if;
+ -- end of the bus cycle
+ wb_cyc_t <= '0';
+ wishbone_current_state <= WB_IDLE;
end if;
when others =>
@@ -471,6 +484,7 @@ begin
wb_dat_o <= wb_dat_o_t;
wb_ack_t <= wb_ack_i;
wb_stall_t <= wb_stall_i;
+ wb_err_t <= wb_err_i;
end behaviour;
--
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