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Tomasz Wlostowski authored
- rework simdrv_defs into a package - use SV queues instead of dynamic arrays in the APIs (as they resemble C++'s std::vector a bit more, hence are more convenient to use) - added AXI4 BFMs from the PULP project library - added a bunch of simulation drivers (for the VUART & LM32 MCS cores) - added a trivial unit test/logging "framework" (see logger.svh) Note these changes will break your legacy testbenches, here's how to fix the most common issues: - Replace the includes of simdrv_defs.svh indo an include of "gencores_sim_defs.svh" followed by import of gencores_sim_pkg package - If your code uses CBusAccessor::readm/writem, change the addr/data parameters to use SV queues instead of dynamic arrays
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axi | ||
drivers | ||
gc_fsm_watchdog | ||
regs | ||
vhdl | ||
wb_i2c_bridge | ||
wishbone | ||
Manifest.py | ||
gencores_sim_defs.svh | ||
gencores_sim_pkg.sv | ||
logger.svh | ||
onewire_slave_model.v | ||
serializable.svh | ||
simdrv_wb_spi.svh |