sim: start redesign/cleanup of the SystemVerilog testing code:
- rework simdrv_defs into a package - use SV queues instead of dynamic arrays in the APIs (as they resemble C++'s std::vector a bit more, hence are more convenient to use) - added AXI4 BFMs from the PULP project library - added a bunch of simulation drivers (for the VUART & LM32 MCS cores) - added a trivial unit test/logging "framework" (see logger.svh) Note these changes will break your legacy testbenches, here's how to fix the most common issues: - Replace the includes of simdrv_defs.svh indo an include of "gencores_sim_defs.svh" followed by import of gencores_sim_pkg package - If your code uses CBusAccessor::readm/writem, change the addr/data parameters to use SV queues instead of dynamic arrays
Showing
sim/Manifest.py
0 → 100644
sim/axi/assign.svh
0 → 100644
This diff is collapsed.
sim/axi/axi_intf.sv
0 → 100644
This diff is collapsed.
sim/axi/axi_pkg.sv
0 → 100644
This diff is collapsed.
sim/axi/axi_test.sv
0 → 100644
This diff is collapsed.
sim/axi/axi_utils.sv
0 → 100644
sim/axi/rand_id_queue.sv
0 → 100644
sim/axi/typedef.svh
0 → 100644
This diff is collapsed.
sim/drivers/Manifest.py
0 → 100644
sim/drivers/vuart_driver.sv
0 → 100644
sim/gencores_sim_defs.svh
0 → 100644
sim/gencores_sim_pkg.sv
0 → 100644
sim/logger.svh
0 → 100644
This diff is collapsed.
sim/serializable.svh
0 → 100644
sim/simdrv_defs.svh
deleted
100644 → 0
This diff is collapsed.
File moved
Please
register
or
sign in
to comment