generate_cdc_constraints.tcl creates faulty constraints with path segmentation
In some scenarios the
tools/generate_cdc_constraints.tcl script creates constraints that will trigger critical implementation warnings in Vivado:
[Constraints 18-515] set_max_delay: Path segmentation by forcing 'some_starting_regs/O' to be timing startpoint. [/path/to/gencores_constraints.xdc:1] Resolution: Use valid startpoint to avoid path segmentation such as the clock pin of a register.
This is a legitimate warning and such constraints will ignore the source clock skew and insertion delays, while still taking into account the destination clock skew.
The proper startpoint is always a
CLK clock input of a sequential element.
More info about the path segmentation can be found in Xilinx documentation, specifically UG903 "Vivado Design Suite User Guide: Using Constraints" -> Ch.5 Timing Exceptions -> Path Segmentation
It's true that generated constraints contain
-datapath_only switch that should ignore src/dst clock skew, but it's not clear how path segmentation interacts with that switch. Moreover, having N critical warning after implementation is always bad and may obfuscate other issues for anyone analyzing their design.