The module gc_sync, at least on master and proposed-master, has the RLOC attribute on sync0 and sync1signals, as shown below:

attribute rloc          : string;
attribute rloc of sync0 : signal is "X0Y0";
attribute rloc of sync1 : signal is "X0Y0";

Looking at my synthesis/implementation reports on Vivado 2018.3 I couldn't find any mention of this attribute being found and no warnings, as well. Looking at the implemented design it doesn't look like this FFs are placed in X0Y0. So, this attribute doesn't appear to be working. If it indeed worked I think it could lead to problems, as X0Y0 is just too specific for such a generic module like a 2-stage synchronizer.

Lucas