Commit dbcee000 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wishbone/wb_vic: more verbose documentation

parent 10071c21
......@@ -12,7 +12,7 @@ peripheral {
field {
name = "VIC Enable";
description = "1: enables VIC operation\n0: disables VIC operation";
description = "- 1: enables VIC operation\n- 0: disables VIC operation";
prefix = "ENABLE";
type = BIT;
access_dev = READ_ONLY;
......@@ -21,7 +21,7 @@ peripheral {
field {
name = "VIC output polarity";
description = "1: IRQ output is active high\n0: IRQ output is active low";
description = "- 1: IRQ output is active high\n- 0: IRQ output is active low";
prefix = "POL";
type = BIT;
access_dev = READ_ONLY;
......@@ -30,8 +30,7 @@ peripheral {
field {
name = "Emulate Edge sensitive output";
description = "1: Forces a low pulse of EMU_WIDTH clock cycles at each write to EOIR. Useful for edge-only IRQ controllers such as Gennum.\
0: Normal IRQ master line behavior";
description = "- 1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Useful for edge-only IRQ controllers such as Gennum.\n- 0: Normal IRQ master line behavior";
prefix = "EMU_EDGE";
type = BIT;
access_dev = READ_ONLY;
......@@ -40,6 +39,7 @@ peripheral {
field {
name = "Emulated Edge pulse timer";
description = "Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.";
prefix = "EMU_LEN";
type = SLV;
size = 16;
......@@ -54,7 +54,7 @@ peripheral {
field {
name = "Raw interrupt status";
description = "Each bit reflects the current state of corresponding IRQ input line.\nread 1: interrupt line is currently active\nread 0: interrupt line is inactive";
description = "Each bit reflects the current state of corresponding IRQ input line.\n- read 1: interrupt line is currently active\n- read 0: interrupt line is inactive";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
......@@ -68,7 +68,7 @@ peripheral {
field {
name = "Enable IRQ";
description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
......@@ -80,7 +80,7 @@ peripheral {
field {
name = "Disable IRQ";
description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
......@@ -92,7 +92,7 @@ peripheral {
field {
name = "IRQ disabled/enabled";
description = "Read 1: interrupt associated with bitfield is enabled\nRead 0: interrupt is disabled";
description = "- read 1: interrupt associated with read bit is enabled\n- read 0: interrupt is disabled";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -131,7 +131,7 @@ peripheral {
field {
name = "End of Interrupt";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s).";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.";
type = PASS_THROUGH;
size = 32;
};
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment