serial_lcd: generic_dpram dual_clock generic matters now -- it was wrong

d2ac70a7 · Wesley W. Terpstra · 0cd877cf · d2ac70a7
Commit d2ac70a7 authored Mar 05, 2013 by Wesley W. Terpstra
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wb_serial_lcd.vhd modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd +1 -1

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--- a/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
+++ b/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
@@ -63,7 +63,7 @@ begin
      g_data_width       => 32,
      g_size             => 2**c_bits,
      g_with_byte_enable => true,
-      g_dual_clock       => false)
+      g_dual_clock       => true)
    port map(
      clka_i => slave_clk_i,
      bwea_i => slave_i.sel,