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Platform-independent core collection
Commit c51e5109 authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'greg-proposed_master' into 'proposed_master' 

Fixes to the latest proposed_master merge

See merge request !11
parents b34b5008 4974967a
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Showing with 5 additions and 4 deletions
modules/genrams/common/inferred_sync_fifo.vhd
View file @ c51e5109
...@@ -91,7 +91,7 @@ architecture syn of inferred_sync_fifo is ...@@ -91,7 +91,7 @@ architecture syn of inferred_sync_fifo is
begin -- syn begin -- syn
legacy_mode_check: assert g_show_ahead = false or g_show_ahead_legacy_mode = false legacy_mode_check: assert g_show_ahead = false or g_show_ahead_legacy_mode = false
report legacy_mode_check'instance_name & ": show-ahead enabled for sync FIFO in " & report "inferred_sync_fifo: show-ahead enabled for sync FIFO in " &
"legacy mode. In this mode, the full flag is asserted at g_SIZE-1. if you want the " & "legacy mode. In this mode, the full flag is asserted at g_SIZE-1. if you want the " &
"full flag to be asserted at g_SIZE, then disable g_SHOW_AHEAD_LEGACY_MODE." "full flag to be asserted at g_SIZE, then disable g_SHOW_AHEAD_LEGACY_MODE."
severity NOTE; severity NOTE;
......
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd
View file @ c51e5109
...@@ -19,6 +19,7 @@ entity fine_pulse_gen_kintex7 is ...@@ -19,6 +19,7 @@ entity fine_pulse_gen_kintex7 is
clk_par_i : in std_logic; clk_par_i : in std_logic;
clk_serdes_i : in std_logic; clk_serdes_i : in std_logic;
rst_serdes_i : in std_logic;
rst_sys_n_i : in std_logic; rst_sys_n_i : in std_logic;
cont_i : in std_logic; cont_i : in std_logic;
...@@ -188,7 +189,7 @@ begin ...@@ -188,7 +189,7 @@ begin
OQ => dout_nodelay, OQ => dout_nodelay,
TBYTEIN => '0', TBYTEIN => '0',
TCE => '0', TCE => '0',
RST => rst); RST => rst_serdes_i);
gen_with_odelay : if g_use_odelay generate gen_with_odelay : if g_use_odelay generate
...@@ -211,7 +212,7 @@ begin ...@@ -211,7 +212,7 @@ begin
INC => '0', INC => '0',
ODATAIN => dout_predelay, ODATAIN => dout_predelay,
LD => odelay_load, LD => odelay_load,
REGRST => rst, REGRST => rst_serdes_i,
LDPIPEEN => '0', LDPIPEEN => '0',
CNTVALUEIN => odelay_ntaps, CNTVALUEIN => odelay_ntaps,
CINVCTRL => '0' CINVCTRL => '0'
......
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ c51e5109
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
...@@ -47,7 +48,6 @@ entity wb_simple_uart is ...@@ -47,7 +48,6 @@ entity wb_simple_uart is
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024; g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0 g_PRESET_BCR : integer := 0
); );
port ( port (
......
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