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Platform-independent core collection
Commit c33d3885 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Made errors reported by the crossbar prettier.

parent 7782095f
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Showing with 65 additions and 14 deletions
modules/wishbone/wb_crossbar/xwb_crossbar.vhd
View file @ c33d3885
......@@ -83,17 +83,17 @@ architecture rtl of xwb_crossbar is
for j in i+1 to g_num_slaves-1 loop
assert not (((c_mask(i) and c_mask(j)) and (c_address(i) xor c_address(j))) = zero)
report "Address ranges must be distinct (slaves " &
Integer'image(i) & "[" & Integer'image(to_integer(unsigned(c_address(i)))) & "/" &
Integer'image(to_integer(unsigned(c_mask(i)))) & "] & " &
Integer'image(j) & "[" & Integer'image(to_integer(unsigned(c_address(j)))) & "/" &
Integer'image(to_integer(unsigned(c_mask(j)))) & "])"
Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
f_bits2string(c_mask(i)) & "] & " &
Integer'image(j) & "[" & f_bits2string(c_address(j)) & "/" &
f_bits2string(c_mask(j)) & "])"
severity Failure;
end loop;
end loop;
for i in 0 to g_num_slaves-1 loop
report "Mapping slave #" &
Integer'image(i) & "[" & Integer'image(to_integer(unsigned(c_address(i)))) & "/" &
Integer'image(to_integer(unsigned(c_mask(i)))) & "]"
Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
f_bits2string(c_mask(i)) & "]"
severity Note;
end loop;
return true;
......
modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
View file @ c33d3885
......@@ -24,12 +24,23 @@ end xwb_sdb_crossbar;
architecture rtl of xwb_sdb_crossbar is
alias c_layout : t_sdb_record_array(g_num_slaves-1 downto 0) is g_layout;
-- Pretty print device name
function f_trim(s : string) return string is
variable cut : natural;
begin
byte : for i in s'length downto 1 loop
cut := i;
exit byte when s(i) /= ' ';
end loop;
return s(1 to cut);
end f_trim;
-- Step 1. Place the SDB ROM on the bus
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
-- Step 2. Find the size of the bus
......@@ -40,7 +51,7 @@ architecture rtl of xwb_sdb_crossbar is
begin
-- The SDB block must be aligned
assert (g_sdb_addr and std_logic_vector(to_unsigned(c_rom_bytes - 1, c_wishbone_address_width))) = zero
report "SDB address is not aligned. This is not supported by the crossbar."
report "SDB address is not aligned (" & f_bits2string(g_sdb_addr) & "). This is not supported by the crossbar."
severity Failure;
if not g_wraparound then
......@@ -82,13 +93,13 @@ architecture rtl of xwb_sdb_crossbar is
-- Range must be valid
assert unsigned(sdb_component.addr_first) <= unsigned(sdb_component.addr_last)
report "Wishbone slave device #" & Integer'image(i) & " (" & sdb_component.product.name & ") wbd_begin address must precede wbd_end address."
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") must precede sdb_component.addr_last address (" & f_bits2string(sdb_component.addr_last) & ")."
severity Failure;
-- Address must fit
extend(c_wishbone_address_width-1 downto 0) := unsigned(result(i));
assert unsigned(sdb_component.addr_first) = extend
report "Wishbone slave device #" & Integer'image(i) & " (" & sdb_component.product.name & ") wbd_begin does not fit in t_wishbone_address."
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & " does not fit in t_wishbone_address."
severity Failure;
end loop;
return result;
......@@ -107,7 +118,7 @@ architecture rtl of xwb_sdb_crossbar is
-- size must be of the form 000000...00001111...1
assert (size and (size + to_unsigned(1, 64))) = zero
report "Wishbone slave device #" & Integer'image(i) & " (" & sdb_component.product.name & ") has an address range size that is not a power of 2 minus one (" & Integer'image(to_integer(size)) & "). This is not supported by the crossbar."
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") has an address range that is not a power of 2 minus one (" & f_bits2string(std_logic_vector(size)) & "). This is not supported by the crossbar."
severity Warning;
-- fix the size up to the form 000...0001111...11
......@@ -117,7 +128,7 @@ architecture rtl of xwb_sdb_crossbar is
-- the base address must be aligned to the size
assert (unsigned(sdb_component.addr_first) and size) = zero
report "Wishbone slave device #" & Integer'image(i) & " (" & sdb_component.product.name & ") wbd_begin address is not aligned. This is not supported by the crossbar."
report "Wishbone slave device #" & Integer'image(i) & " (" & f_trim(sdb_component.product.name) & ") sdb_component.addr_first (" & f_bits2string(sdb_component.addr_first) & ") is not aligned. This is not supported by the crossbar."
severity Failure;
size := c_bus_end - size;
......
modules/wishbone/wishbone_pkg.vhd
View file @ c33d3885
......@@ -74,6 +74,7 @@ package wishbone_pkg is
-- A generally useful function.
function f_ceil_log2(x : natural) return natural;
function f_bits2string(s : std_logic_vector) return string;
------------------------------------------------------------------------------
-- SDB declaration
......@@ -765,8 +766,8 @@ package body wishbone_pkg is
is
variable result : t_sdb_record;
variable first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
variable child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
......@@ -883,4 +884,43 @@ package body wishbone_pkg is
return result;
end f_xwb_dpram;
function f_bits2string(s : std_logic_vector) return string is
--- extend length to full hex nibble
variable result : string((s'length+7)/4 downto 1);
variable s_norm : std_logic_vector(result'length*4-1 downto 0) := (others=>'0');
variable cut : natural;
begin
s_norm(s'length-1 downto 0) := s;
for i in result'length-1 downto 0 loop
case s_norm(i*4+3 downto i*4) is
when "0000" => result(i+1) := '0';
when "0001" => result(i+1) := '1';
when "0010" => result(i+1) := '2';
when "0011" => result(i+1) := '3';
when "0100" => result(i+1) := '4';
when "0101" => result(i+1) := '5';
when "0110" => result(i+1) := '6';
when "0111" => result(i+1) := '7';
when "1000" => result(i+1) := '8';
when "1001" => result(i+1) := '9';
when "1010" => result(i+1) := 'a';
when "1011" => result(i+1) := 'b';
when "1100" => result(i+1) := 'c';
when "1101" => result(i+1) := 'd';
when "1110" => result(i+1) := 'e';
when "1111" => result(i+1) := 'f';
when others => result(i+1) := 'X';
end case;
end loop;
-- trim leading 0s
strip : for i in result'length downto 1 loop
cut := i;
exit strip when result(i) /= '0';
end loop;
return "0x" & result(cut downto 1);
end f_bits2string;
end wishbone_pkg;
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