sim: uploaded Wishbone BFMs

bf7af1d8 · Tomasz Wlostowski · 41cdcfad · bf7af1d8 · bf7af1d8 · bf7af1d8
Commit bf7af1d8 authored Jan 31, 2012 by Tomasz Wlostowski
8 changed files
--- a/sim/if_wb_link.svh
+++ b/sim/if_wb_link.svh
+
+interface IWishboneLink;
+
+   parameter g_data_width 	   = 32;
+   parameter g_addr_width 	   = 32;
+   
+
+   wire [g_addr_width - 1 : 0] adr;
+   wire [g_data_width - 1 : 0] dat_o;
+   wire [g_data_width - 1 : 0] dat_i;
+   wire [(g_data_width/8)-1 : 0] sel; 
+   wire ack;
+   wire stall;
+   wire err;
+   wire rty;
+   wire	cyc;
+   wire stb;
+   wire we;
+   
+   modport slave
+     (
+      output adr,
+      output dat_o,
+      input dat_i,
+      output sel,
+      output cyc,
+      output stb,
+      output we,
+      input ack,
+      input stall,
+      input err,
+      input rty
+      );
+
+   modport master
+     (
+      input adr,
+      input dat_o,
+      output dat_i,
+      input sel,
+      input cyc,
+      input stb,
+      input we,
+      output ack,
+      output stall,
+      output err,
+      output rty
+      );
+
+endinterface // IWishboneLink
--- a/sim/if_wb_master.svh
+++ b/sim/if_wb_master.svh
--- a/sim/if_wb_slave.svh
+++ b/sim/if_wb_slave.svh
+`ifndef __IF_WISHBONE_SLAVE_SVH
+`define __IF_WISHBONE_SLAVE_SVH
+
+`timescale 1ns/1ps
+
+`include "if_wishbone_types.svh"
+
+
+
+interface IWishboneSlave
+  (
+   input clk_i,
+   input rst_n_i
+   );
+
+   parameter g_addr_width  = 32;
+   parameter g_data_width  = 32;
+   
+   
+   wire [g_addr_width - 1: 0] adr;
+   wire [g_data_width - 1: 0] dat_i;
+   wire [(g_data_width/8)-1 : 0] sel; 
+   logic [g_data_width - 1 : 0] dat_o;
+   logic ack;
+   logic stall;
+   logic err;
+   logic rty;
+   wire	cyc;
+   wire stb;
+   wire we;
+
+
+
+   time last_access_t  = 0;
+
+   modport slave
+     (
+      input adr,
+      input dat_o,
+      input sel,
+      input cyc,
+      input stb,
+      input we,
+      output ack,
+      output dat_i,
+      output stall,
+      output err,
+      output rty
+      );
+
+   wb_cycle_t c_queue[$];
+   wb_cycle_t current_cycle;
+
+   reg cyc_prev;
+   int trans_index;
+   int first_transaction;
+
+   struct {
+      wb_cycle_type_t mode;
+      int gen_random_stalls;
+      int stall_min_duration;
+      int stall_max_duration;
+      real stall_prob;
+   } settings;
+
+
+   function automatic int _poll(); return poll(); endfunction
+   task automatic _get(ref wb_cycle_t xfer); get(xfer); endtask
+
+   class CIWBSlaveAccessor extends CWishboneAccessor;
+
+      function automatic int poll();
+         return _poll();
+      endfunction
+      
+      task get(ref wb_cycle_t xfer);
+         _get(xfer);
+      endtask
+      
+      task clear();
+      endtask // clear
+      
+   endclass // CIWBSlaveAccessor
+   
+
+   function CIWBSlaveAccessor get_accessor();
+      CIWBSlaveAccessor tmp;
+      tmp  = new;
+      return tmp;
+   endfunction // get_accessor
+      
+   
+   function automatic int poll();
+      return c_queue.size() != 0;
+   endfunction // poll
+      
+   task automatic get(ref wb_cycle_t xfer);
+      while(c_queue.size() <= 0)
+	@(posedge clk_i);
+	
+      xfer 			    = c_queue.pop_front();
+   endtask // pop_cycle
+
+
+   always@(posedge clk_i) cyc_prev <= cyc;
+   wire cyc_start 		    = !cyc_prev && cyc;
+   wire cyc_end 		    = cyc_prev && !cyc;
+
+
+   task gen_random_stalls();
+      static int stall_remaining  = 0;
+      static int seed             = 0;
+
+//      $display("stallr: %d\n", stall_remaining);
+      
+      if(settings.gen_random_stalls && (probability_hit(settings.stall_prob) || stall_remaining > 0))
+        begin
+           
+           if(stall_remaining == 0)
+             stall_remaining           = $dist_uniform(seed, 
+                                                    settings.stall_min_duration,
+                                                    settings.stall_max_duration);
+           if(stall_remaining) 
+             stall_remaining--;
+           
+	   stall <= 1;
+        end else
+	  stall <= 0;
+      
+	
+   endtask // gen_random_stalls
+
+   function automatic int count_ones(int x, int n_bits);
+      int i, cnt;
+      cnt  = 0;
+      for(i=0;i<n_bits;i++) if(x & (1<<i)) cnt ++;
+      return cnt;
+   endfunction
+
+   function automatic int count_leading_zeroes(int x, int n_bits);
+     int i;
+      for(i=0;i<n_bits && !(x & (1<<i)); i++);
+      return i;
+   endfunction // count_leading_zeroes
+
+    function automatic int count_trailing_zeroes(int x, int n_bits);
+     int i;
+      for(i=n_bits-1;i>=0 && !(x & (1<<i)); i--);
+      return (n_bits-1-i);
+   endfunction
+
+   
+   task pipelined_fsm();
+
+      if(settings.gen_random_stalls)
+	gen_random_stalls();
+      else
+        stall               <= 0;
+      
+/* -----\/----- EXCLUDED -----\/-----
+      if(cyc) begin
+
+	 end else
+	   stall            <= 0;
+ -----/\----- EXCLUDED -----/\----- */
+      
+      if(cyc_start) begin
+	 current_cycle.data  = {};
+	 trans_index        <= 0;
+	 first_transaction   = 1;
+      end
+
+      if(cyc_end) begin
+	 c_queue.push_back(current_cycle);
+      end
+
+      if(stb && we && !stall && cyc) begin
+         int oc, lzc, tzc;
+         
+	 wb_xfer_t d;
+         
+         oc      = count_ones(sel, g_data_width/8);
+         lzc     = count_leading_zeroes(sel, g_data_width/8);
+         tzc     = count_trailing_zeroes(sel, g_data_width/8);
+	 d.a     = adr * (g_data_width / 8);
+         d.size  = oc;
+	 d.d     = (dat_i>>(8*lzc)) & ((1<<(oc*8)) -1);
+         
+         if(lzc + tzc + oc != g_data_width/8)
+           $error("IWishboneSlave [write a %x d %x sel %x]: non-contiguous sel", adr, dat_i, sel);
+         
+	 d.sel [g_data_width/8-1:0] = sel;
+     
+	 current_cycle.data.push_back(d);
+
+//	$display("ifWb:[%d] write a %x d %x sel %x",current_cycle.data.size(), adr, dat_i, sel);
+	 ack <= 1;
+	 
+      end else if(stb && !we && !stall) begin
+//	 $error("Sorry, no pipelined read for slave yet implemented");
+	ack 			<= 0;
+      end else
+	ack 			<= 0;
+
+
+      
+   endtask // pipelined_fsm
+      
+   always@(posedge clk_i)
+     begin
+	if(!rst_n_i)
+	  begin
+	     c_queue 		 = {};
+	     current_cycle.data  = {};
+	     trans_index 	 = 0;
+	     ack 		<= 0;
+	     rty 		<= 0;
+	     err 		<= 0;
+	     dat_o 		<= 0;
+	     stall 		<= 0;
+	     
+	  end else begin
+	     if(settings.mode == PIPELINED)
+		  pipelined_fsm();
+	     end
+     end
+   
+   initial begin
+      settings.mode                = PIPELINED;
+      settings.gen_random_stalls   = 1;
+      settings.stall_prob          = 0.1;
+      settings.stall_min_duration  = 1;
+      settings.stall_max_duration  = 2;
+      
+   end
+   
+   
+   
+endinterface // IWishboneSlave
+
+`endif
\ No newline at end of file
--- a/sim/if_wishbone_accessor.svh
+++ b/sim/if_wishbone_accessor.svh
+`ifndef IF_WISHBONE_ACCESSOR_SV
+`define IF_WISHBONE_ACCESSOR_SV
+
+`include "if_wishbone_types.svh"
+
+virtual class CWishboneAccessor extends CBusAccessor;
+
+   static int _null  = 0;
+   protected wb_cycle_type_t m_cycle_type;
+
+   function new();
+      m_cycle_type  = CLASSIC;
+   endfunction // new
+
+   virtual task set_mode(wb_cycle_type_t mode);
+      m_cycle_type  = mode;
+   endtask // set_mode
+   
+   
+   // [slave only] checks if there are any transactions in the queue 
+   virtual function automatic int poll();
+      return 0;
+   endfunction // poll
+
+   // [slave only] adds a simulation event (e.g. a forced STALL, RETRY, ERROR)
+   // evt = event type (STALL, ERROR, RETRY)
+   // behv = event behavior: DELAYED - event occurs after a predefined delay (dly_start)
+   //                        RANDOM - event occurs randomly with probability (prob)
+   // These two can be combined (random events occuring after a certain initial delay)
+   // DELAYED events can be repeated (rep_rate parameter)
+   virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);
+
+   endtask // add_event
+
+
+   // [slave only] gets a cycle from the queue
+   virtual task get(ref wb_cycle_t xfer);
+      
+   endtask // get
+
+   // [master only] executes a cycle and returns its result
+   virtual task put(ref wb_cycle_t xfer);
+
+   endtask // put
+   
+   virtual function int idle();
+      return 1;
+   endfunction // idle
+   
+   // [master only] generic write(s), blocking
+   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);
+      wb_cycle_t cycle;
+      int i;
+
+      cycle.ctype  = m_cycle_type;
+      cycle.rw  = 1'b1;
+      
+      for(i=0;i < addr.size(); i++)
+        begin
+           wb_xfer_t xfer;
+           xfer.a     = addr[i];
+           xfer.d     = data[i];
+           xfer.size  = size;
+           cycle.data.push_back(xfer);
+        end
+
+//      $display("DS: %d", cycle.data.size());
+      
+      put(cycle);
+      get(cycle);
+      result  = cycle.result;
+      
+   endtask // write
+
+   // [master only] generic read(s), blocking
+   virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);
+      wb_cycle_t cycle;
+      int i;
+
+      cycle.ctype  = m_cycle_type;
+      cycle.rw  = 1'b0;
+      
+      for(i=0;i < addr.size(); i++)
+        begin
+           wb_xfer_t xfer;
+           xfer.a     = addr[i];
+           xfer.size  = size;
+           cycle.data.push_back(xfer);
+        end
+
+      put(cycle);
+      get(cycle);
+
+      for(i=0;i < addr.size(); i++)
+        data[i]  = cycle.data[i].d;
+      
+      result     = cycle.result;
+
+   endtask // readm
+
+   virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
+      uint64_t aa[], da[];
+      aa     = new[1];
+      da     = new[1];
+      aa[0]  = addr;
+      readm(aa, da, size, result);
+      data  = da[0];
+   endtask
+
+   virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);
+      uint64_t aa[], da[];
+      aa     = new[1];
+      da     = new[1];
+      
+      aa[0]  = addr;
+      da[0]  = data;
+      writem(aa, da, size, result);
+   endtask
+   
+endclass // CWishboneAccessor
+
+static int seed = 0;
+
+function automatic int probability_hit(real prob);
+   real rand_val;
+   rand_val 	= real'($dist_uniform(seed, 0, 1000)) / 1000.0;
+      
+   if(rand_val < prob)
+     return 1;
+   else
+     return 0;
+    
+endfunction // probability_hit
+
+
+`endif //  `ifndef IF_WISHBONE_ACCESSOR_SV
+
--- a/sim/if_wishbone_defs.svh
+++ b/sim/if_wishbone_defs.svh
+//
+// Title          : Software Wishbone master unit for testbenches
+//
+// File           : wishbone_master_tb.v
+// Author         : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+// Created        : Tue Mar 23 12:19:36 2010
+// Standard       : Verilog 2001
+//
+
+`ifndef __IF_WB_DEFS_SV
+`define __IF_WB_DEFS_SV
+
+`include "simdrv_defs.sv"
+
+typedef enum 
+{
+  R_OK = 0,
+  R_ERROR,
+  R_RETRY
+} wb_cycle_result_t;
+
+typedef enum
+{
+  CLASSIC = 0,
+  PIPELINED = 1
+} wb_cycle_type_t;
+
+typedef struct {
+   uint64_t a;
+   uint64_t d;
+   bit[7:0] sel;
+   int size;
+} wb_xfer_t;
+
+typedef struct {
+   int rw;
+   wb_cycle_type_t ctype;
+   wb_xfer_t data[$];
+   wb_cycle_result_t result;
+} wb_cycle_t;
+
+
+virtual class CWishboneAccessor;
+
+   virtual function automatic int poll();
+      return 0;
+   endfunction // poll
+      
+   virtual task get(output wb_cycle_t xfer);
+   endtask // get
+   
+   virtual task put(input wb_cycle_t xfer);
+   endtask // put
+   
+   virtual function int idle();
+      return 0;
+   endfunction // idle
+   
+   virtual task clear(); endtask
+
+endclass // CWishboneAccessor
+
+int seed  = 0;
+
+   function automatic int probability_hit(real prob);
+     real rand_val;
+      rand_val 	= real'($dist_uniform(seed, 0, 1000)) / 1000.0;
+      
+      if(rand_val < prob)
+	return 1;
+      else
+	return 0;
+    
+   endfunction // probability_hit
+
+
+`endif //  `ifndef __IF_WB_DEFS_SV
--- a/sim/if_wishbone_types.svh
+++ b/sim/if_wishbone_types.svh
+//
+// Title          : Pipelined Wishbone BFM - type definitions
+//
+// File           : if_wishbone_types.sv
+// Author         : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+// Created        : Tue Mar 23 12:19:36 2010
+// Standard       : Verilog 2001
+//
+
+`ifndef __IF_WB_TYPES_SVH
+`define __IF_WB_TYPES_SVH
+
+`include "simdrv_defs.svh"
+
+typedef enum 
+{
+  R_OK = 0,
+  R_ERROR,
+  R_RETRY
+} wb_cycle_result_t;
+
+typedef enum
+{
+  CLASSIC = 0,
+  PIPELINED = 1
+} wb_cycle_type_t;
+
+typedef enum {
+  WORD = 0,
+  BYTE = 1
+} wb_address_granularity_t;
+
+typedef struct {
+   uint64_t a;
+   uint64_t d;
+   int size;
+   bit [7:0] sel;
+} wb_xfer_t;
+
+typedef struct  {
+   int rw;
+   wb_cycle_type_t ctype;
+   wb_xfer_t data[$];
+   wb_cycle_result_t result;
+} wb_cycle_t;
+
+typedef enum  
+ {
+  RETRY = 0,
+  STALL,
+  ERROR
+} wba_sim_event_t;
+
+typedef enum
+{
+  RANDOM = (1<<0),
+  DELAYED = (1<<1)
+ } wba_sim_behavior_t;
+
+`endif //  `ifndef __IF_WB_TYPES_SVH
+
--- a/sim/regs/xloader_regs.vh
+++ b/sim/regs/xloader_regs.vh
+`define ADDR_XLDR_CSR                  4'h0
+`define XLDR_CSR_START_OFFSET 0
+`define XLDR_CSR_START 32'h00000001
+`define XLDR_CSR_DONE_OFFSET 1
+`define XLDR_CSR_DONE 32'h00000002
+`define XLDR_CSR_ERROR_OFFSET 2
+`define XLDR_CSR_ERROR 32'h00000004
+`define XLDR_CSR_BUSY_OFFSET 3
+`define XLDR_CSR_BUSY 32'h00000008
+`define XLDR_CSR_MSBF_OFFSET 4
+`define XLDR_CSR_MSBF 32'h00000010
+`define XLDR_CSR_SWRST_OFFSET 5
+`define XLDR_CSR_SWRST 32'h00000020
+`define XLDR_CSR_CLKDIV_OFFSET 8
+`define XLDR_CSR_CLKDIV 32'h00003f00
+`define ADDR_XLDR_FIFO_R0              4'h4
+`define XLDR_FIFO_R0_XSIZE_OFFSET 0
+`define XLDR_FIFO_R0_XSIZE 32'h00000003
+`define XLDR_FIFO_R0_XLAST_OFFSET 2
+`define XLDR_FIFO_R0_XLAST 32'h00000004
+`define ADDR_XLDR_FIFO_R1              4'h8
+`define XLDR_FIFO_R1_XDATA_OFFSET 0
+`define XLDR_FIFO_R1_XDATA 32'hffffffff
+`define ADDR_XLDR_FIFO_CSR             4'hc
+`define XLDR_FIFO_CSR_FULL_OFFSET 16
+`define XLDR_FIFO_CSR_FULL 32'h00010000
+`define XLDR_FIFO_CSR_EMPTY_OFFSET 17
+`define XLDR_FIFO_CSR_EMPTY 32'h00020000
+`define XLDR_FIFO_CSR_USEDW_OFFSET 0
+`define XLDR_FIFO_CSR_USEDW 32'h000000ff
--- a/sim/simdrv_defs.svh
+++ b/sim/simdrv_defs.svh
+`ifndef SIMDRV_DEFS_SV
+ `define SIMDRV_DEFS_SV 1
+
+typedef longint unsigned uint64_t;
+typedef int unsigned uint32_t;
+typedef shortint unsigned uint16_t;
+
+
+
+typedef uint64_t u64_array_t[];
+typedef byte byte_array_t[];
+
+
+
+
+virtual class CBusAccessor;
+   static int _null  = 0;
+   
+   pure virtual task writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
+   pure virtual task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
+
+   virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
+      int res;
+      uint64_t aa[1], da[];
+
+      da= new[1];
+      
+      aa[0]  = addr;
+      readm(aa, da, size, res);
+      data  = da[0];
+   endtask
+
+
+   virtual task write(uint64_t addr, uint64_t data, input int size = 4, ref int result = _null);
+      uint64_t aa[1], da[1];
+      aa[0]  = addr;
+      da[0]  = data;
+      writem(aa, da, size, result);
+   endtask
+
+endclass // CBusAccessor
+
+class CSimUtils;
+   
+   static function automatic u64_array_t pack(byte x[], int size, int big_endian = 1);
+      u64_array_t tmp;
+      int i, j;
+      int nwords, nbytes;
+
+      nwords  = (x.size() + size - 1) / size;
+      tmp     = new [nwords];
+
+      for(i=0;i<nwords;i++)
+        begin      
+           uint64_t d;
+           d         =0;
+           nbytes    = (x.size() - i * nbytes > size ? size : x.size() - i*nbytes);
+           
+           for(j=0;j<nbytes;j++)
+             begin
+                if(big_endian)
+                  d  = d | ((x[i*size+j] << (8*(size-1-j))));
+                else
+                  d  = d | ((x[i*size+j] << (8*j)));
+             end
+
+           
+           tmp[i]    = d;
+        end
+      return tmp;
+      endfunction // pack
+   
+
+   static function automatic byte_array_t unpack(u64_array_t x, int entry_size, int size, int big_endian = 1);
+      byte_array_t tmp;
+      int i, n;
+
+      tmp  = new[size];
+      n    = 0;
+      i    = 0;
+      
+      
+      while(n < size)
+        begin
+           tmp[n]  = x[i] >> (8*(entry_size-1 - (n % entry_size)));
+           
+           n++;
+           if(n % entry_size == 0)
+             i++;
+        end
+
+      return tmp;
+   endfunction // unpack
+   
+  
+   
+
+endclass // CSimUtils
+
+static CSimUtils SimUtils;
+
+
+
+`endif
\ No newline at end of file