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Platform-independent core collection
Commit b80cef2b authored by Dimitris Lampridis's avatar Dimitris Lampridis
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tools: add verilog support to sourceid 

Also make it possible to define the name of the project with a
command-line argument.
parent 3ca2f67c
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Showing with 53 additions and 14 deletions
tools/gen_sourceid.py
View file @ b80cef2b
# Script to generate the sourceid_<project>_pkg.vhd file
# Script to generate the HDL sourceid information for a given project
# Local parameter: project
# Note: this script differs from the (similar) gen_buildinfo.py in that it produces std_logic
# vectors with versioning info to be embedded in the metadata, while buildinfo produces a string
# that focuses more on when/how/who built the bitstream.
with open("sourceid_{}_pkg.vhd".format(project), "w") as f:
import argparse
import sys
parser = argparse.ArgumentParser(
description='Generate source ID for given project')
parser.add_argument('-p', '--project',
help = "Project name to use. If not provided, will look for a 'project' local variable.")
parser.add_argument('-l', '--language', choices = ['VHDL','Verilog'], default = 'VHDL',
help = "HDL language for output file. If not provided, defaults to VHDL.")
args = parser.parse_args()
if(args.project):
project = args.project
try:
project
except NameError:
print("""No project defined, make sure you either define your variable
(e.g. like HdlMake does when you source this script),
or that you provide the '-p' argument at run-time.""")
sys.exit(1)
if (args.language) == 'VHDL':
outfile = "sourceid_{}_pkg.vhd".format(project)
comment = "--"
else:
outfile = "sourceid_{}.vh".format(project)
comment = "//"
with open(outfile, "w") as f:
import subprocess
import time
import re
......@@ -39,16 +68,26 @@ with open("sourceid_{}_pkg.vhd".format(project), "w") as f:
# find the sha1 in the project.
sourceid = sourceid[:16] + (16 * '0')
f.write("-- Sourceid for project {}\n".format(project))
f.write("--\n")
f.write("-- This file was automatically generated; do not edit\n")
f.write("\n")
f.write("library ieee;\n")
f.write("use ieee.std_logic_1164.all;\n")
f.write(f"{comment} Sourceid for project {project}\n")
f.write(f"{comment}\n")
f.write(f"{comment} This file was automatically generated; do not edit\n")
f.write("\n")
f.write("package sourceid_{}_pkg is\n".format(project))
f.write(" constant sourceid : std_logic_vector(127 downto 0) :=\n")
f.write(' x"{}";\n'.format(sourceid))
f.write(" constant version : std_logic_vector(31 downto 0) := ")
f.write('x"{:02x}{:02x}{:04x}";\n'.format(major & 0xff, minor & 0xff, patch & 0xffff))
f.write('end sourceid_{}_pkg;\n'.format(project))
if args.language == 'VHDL':
f.write("library ieee;\n")
f.write("use ieee.std_logic_1164.all;\n")
f.write("\n")
f.write("package sourceid_{}_pkg is\n".format(project))
f.write(" constant sourceid : std_logic_vector(127 downto 0) :=\n")
f.write(' x"{}";\n'.format(sourceid))
f.write(" constant version : std_logic_vector(31 downto 0) := ")
f.write('x"{:02x}{:02x}{:04x}";\n'.format(major & 0xff, minor & 0xff, patch & 0xffff))
f.write('end sourceid_{}_pkg;\n'.format(project))
else:
f.write(f"`ifndef SOURCEID_{project.upper()}_H\n")
f.write(f"`define SOURCEID_{project.upper()}_H\n")
f.write("\n")
f.write(f"`define SOURCEID_{project.upper()}_SOURCEID 128'h{sourceid}\n")
f.write(f"`define SOURCEID_{project.upper()}_VERSION 32'h{major:02x}{minor:02x}{patch:04x}\n")
f.write("\n")
f.write(f"`endif // ifndef SOURCEID_{project.upper()}_H\n")
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