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Platform-independent core collection
Commit a472d47f authored by Dimitris Lampridis's avatar Dimitris Lampridis
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genrams: add initial values to rcb and wcb in async fifos to make simulators happier

parent 41a19a4c
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modules/genrams/common/inferred_async_fifo.vhd
View file @ a472d47f
......@@ -115,7 +115,7 @@ architecture syn of inferred_async_fifo is
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem_type := (others => (others => '0'));
signal rcb, wcb : t_counter_block;
signal rcb, wcb : t_counter_block := (others =>(others => '0'));
signal rd_ptr_muxed : t_counter;
......
modules/genrams/common/inferred_async_fifo_dual_rst.vhd
View file @ a472d47f
......@@ -105,7 +105,7 @@ architecture arch of inferred_async_fifo_dual_rst is
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem_type := (others => (others => '0'));
signal rcb, wcb : t_counter_block;
signal rcb, wcb : t_counter_block := (others =>(others => '0'));
signal rd_ptr_muxed : t_counter;
......
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