Skip to content

P
Platform-independent core collection
Commit 9ef0c76a authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

Merge branch '44-wb_uart-new-features' into 'master' 

Addition of 2 bits in status register to clarify if you are using Virtual or Physical UART

See merge request !53
parents 225dd70e 1892accc
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 430 additions and 392 deletions
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @ 9ef0c76a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Fri Oct 16 13:22:41 2020
-- Created : Fri Dec 8 11:12:47 2023
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -29,6 +29,8 @@ package uart_wbgen2_pkg is
sr_tx_fifo_full_i : std_logic;
sr_rx_fifo_overflow_i : std_logic;
sr_rx_fifo_bytes_i : std_logic_vector(15 downto 0);
sr_physical_uart_i : std_logic;
sr_virtual_uart_i : std_logic;
rdr_rx_data_i : std_logic_vector(7 downto 0);
host_tdr_rdy_i : std_logic;
host_rdr_data_i : std_logic_vector(7 downto 0);
......@@ -46,6 +48,8 @@ package uart_wbgen2_pkg is
sr_tx_fifo_full_i => '0',
sr_rx_fifo_overflow_i => '0',
sr_rx_fifo_bytes_i => (others => '0'),
sr_physical_uart_i => '0',
sr_virtual_uart_i => '0',
rdr_rx_data_i => (others => '0'),
host_tdr_rdy_i => '0',
host_rdr_data_i => (others => '0'),
......@@ -80,76 +84,78 @@ package uart_wbgen2_pkg is
cr_rx_fifo_purge_o => '0',
cr_tx_fifo_purge_o => '0'
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component simple_uart_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
end component;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component simple_uart_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
end component;
end package;
package body uart_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
variable tmp: t_uart_in_registers;
begin
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.sr_rx_fifo_supported_i := f_x_to_zero(left.sr_rx_fifo_supported_i) or f_x_to_zero(right.sr_rx_fifo_supported_i);
tmp.sr_tx_fifo_supported_i := f_x_to_zero(left.sr_tx_fifo_supported_i) or f_x_to_zero(right.sr_tx_fifo_supported_i);
tmp.sr_rx_fifo_valid_i := f_x_to_zero(left.sr_rx_fifo_valid_i) or f_x_to_zero(right.sr_rx_fifo_valid_i);
tmp.sr_tx_fifo_empty_i := f_x_to_zero(left.sr_tx_fifo_empty_i) or f_x_to_zero(right.sr_tx_fifo_empty_i);
tmp.sr_tx_fifo_full_i := f_x_to_zero(left.sr_tx_fifo_full_i) or f_x_to_zero(right.sr_tx_fifo_full_i);
tmp.sr_rx_fifo_overflow_i := f_x_to_zero(left.sr_rx_fifo_overflow_i) or f_x_to_zero(right.sr_rx_fifo_overflow_i);
tmp.sr_rx_fifo_bytes_i := f_x_to_zero(left.sr_rx_fifo_bytes_i) or f_x_to_zero(right.sr_rx_fifo_bytes_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
end function;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
variable tmp: t_uart_in_registers;
begin
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.sr_rx_fifo_supported_i := f_x_to_zero(left.sr_rx_fifo_supported_i) or f_x_to_zero(right.sr_rx_fifo_supported_i);
tmp.sr_tx_fifo_supported_i := f_x_to_zero(left.sr_tx_fifo_supported_i) or f_x_to_zero(right.sr_tx_fifo_supported_i);
tmp.sr_rx_fifo_valid_i := f_x_to_zero(left.sr_rx_fifo_valid_i) or f_x_to_zero(right.sr_rx_fifo_valid_i);
tmp.sr_tx_fifo_empty_i := f_x_to_zero(left.sr_tx_fifo_empty_i) or f_x_to_zero(right.sr_tx_fifo_empty_i);
tmp.sr_tx_fifo_full_i := f_x_to_zero(left.sr_tx_fifo_full_i) or f_x_to_zero(right.sr_tx_fifo_full_i);
tmp.sr_rx_fifo_overflow_i := f_x_to_zero(left.sr_rx_fifo_overflow_i) or f_x_to_zero(right.sr_rx_fifo_overflow_i);
tmp.sr_rx_fifo_bytes_i := f_x_to_zero(left.sr_rx_fifo_bytes_i) or f_x_to_zero(right.sr_rx_fifo_bytes_i);
tmp.sr_physical_uart_i := f_x_to_zero(left.sr_physical_uart_i) or f_x_to_zero(right.sr_physical_uart_i);
tmp.sr_virtual_uart_i := f_x_to_zero(left.sr_virtual_uart_i) or f_x_to_zero(right.sr_virtual_uart_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
end function;
end package body;
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ 9ef0c76a
This diff is collapsed.
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @ 9ef0c76a
......@@ -102,6 +102,28 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Physical UART";
description = "Set if the Physical UART is present";
prefix = "PHYSICAL_UART";
type = BIT;
size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Virtual UART";
description = "Set if the Virtual UART is present";
prefix = "VIRTUAL_UART";
type = BIT;
size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 9ef0c76a
......@@ -457,4 +457,8 @@ begin -- arch
regs_in.host_tdr_rdy_i <= not regs_in.sr_rx_rdy_i;
-- Registers to set if the Physical or Virtual UART is present
regs_in.sr_physical_uart_i <= '1' when g_WITH_PHYSICAL_UART else '0';
regs_in.sr_virtual_uart_i <= '1' when g_WITH_VIRTUAL_UART else '0';
end arch;
testbench/wishbone/include/wb_uart_regs.vh
View file @ 9ef0c76a
......@@ -17,6 +17,10 @@
`define UART_SR_RX_FIFO_OVERFLOW 32'h00000080
`define UART_SR_RX_FIFO_BYTES_OFFSET 8
`define UART_SR_RX_FIFO_BYTES 32'h00ffff00
`define UART_SR_PHYSICAL_UART_OFFSET 24
`define UART_SR_PHYSICAL_UART 32'h01000000
`define UART_SR_VIRTUAL_UART_OFFSET 25
`define UART_SR_VIRTUAL_UART 32'h02000000
`define ADDR_UART_BCR 5'h4
`define ADDR_UART_TDR 5'h8
`define UART_TDR_TX_DATA_OFFSET 0
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment