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Platform-independent core collection
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874afe5c
Commit
874afe5c
authored
Dec 08, 2023
by
Konstantinos Blantos
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Plain Diff
Addition of a register to check the endianess in wb_uart
parent
9ef0c76a
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Showing
5 changed files
with
35 additions
and
3 deletions
+35
-3
simple_uart_pkg.vhd
modules/wishbone/wb_uart/simple_uart_pkg.vhd
+5
-2
simple_uart_wb.vhd
modules/wishbone/wb_uart/simple_uart_wb.vhd
+8
-1
simple_uart_wb.wb
modules/wishbone/wb_uart/simple_uart_wb.wb
+17
-0
wb_simple_uart.vhd
modules/wishbone/wb_uart/wb_simple_uart.vhd
+4
-0
wb_uart_regs.vh
testbench/wishbone/include/wb_uart_regs.vh
+1
-0
No files found.
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @
874afe5c
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Fri Dec 8 1
1:12:47
2023
-- Created : Fri Dec 8 1
4:05:32
2023
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
...
@@ -36,6 +36,7 @@ package uart_wbgen2_pkg is
...
@@ -36,6 +36,7 @@ package uart_wbgen2_pkg is
host_rdr_data_i
:
std_logic_vector
(
7
downto
0
);
host_rdr_data_i
:
std_logic_vector
(
7
downto
0
);
host_rdr_rdy_i
:
std_logic
;
host_rdr_rdy_i
:
std_logic
;
host_rdr_count_i
:
std_logic_vector
(
15
downto
0
);
host_rdr_count_i
:
std_logic_vector
(
15
downto
0
);
check_endianess_i
:
std_logic_vector
(
31
downto
0
);
end
record
;
end
record
;
constant
c_uart_in_registers_init_value
:
t_uart_in_registers
:
=
(
constant
c_uart_in_registers_init_value
:
t_uart_in_registers
:
=
(
...
@@ -54,7 +55,8 @@ package uart_wbgen2_pkg is
...
@@ -54,7 +55,8 @@ package uart_wbgen2_pkg is
host_tdr_rdy_i
=>
'0'
,
host_tdr_rdy_i
=>
'0'
,
host_rdr_data_i
=>
(
others
=>
'0'
),
host_rdr_data_i
=>
(
others
=>
'0'
),
host_rdr_rdy_i
=>
'0'
,
host_rdr_rdy_i
=>
'0'
,
host_rdr_count_i
=>
(
others
=>
'0'
)
host_rdr_count_i
=>
(
others
=>
'0'
),
check_endianess_i
=>
(
others
=>
'0'
)
);
);
-- Output registers (WB slave -> user design)
-- Output registers (WB slave -> user design)
...
@@ -155,6 +157,7 @@ package body uart_wbgen2_pkg is
...
@@ -155,6 +157,7 @@ package body uart_wbgen2_pkg is
tmp
.
host_rdr_data_i
:
=
f_x_to_zero
(
left
.
host_rdr_data_i
)
or
f_x_to_zero
(
right
.
host_rdr_data_i
);
tmp
.
host_rdr_data_i
:
=
f_x_to_zero
(
left
.
host_rdr_data_i
)
or
f_x_to_zero
(
right
.
host_rdr_data_i
);
tmp
.
host_rdr_rdy_i
:
=
f_x_to_zero
(
left
.
host_rdr_rdy_i
)
or
f_x_to_zero
(
right
.
host_rdr_rdy_i
);
tmp
.
host_rdr_rdy_i
:
=
f_x_to_zero
(
left
.
host_rdr_rdy_i
)
or
f_x_to_zero
(
right
.
host_rdr_rdy_i
);
tmp
.
host_rdr_count_i
:
=
f_x_to_zero
(
left
.
host_rdr_count_i
)
or
f_x_to_zero
(
right
.
host_rdr_count_i
);
tmp
.
host_rdr_count_i
:
=
f_x_to_zero
(
left
.
host_rdr_count_i
)
or
f_x_to_zero
(
right
.
host_rdr_count_i
);
tmp
.
check_endianess_i
:
=
f_x_to_zero
(
left
.
check_endianess_i
)
or
f_x_to_zero
(
right
.
check_endianess_i
);
return
tmp
;
return
tmp
;
end
function
;
end
function
;
...
...
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @
874afe5c
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : simple_uart_wb.vhd
-- File : simple_uart_wb.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Fri Dec 8 1
1:12:47
2023
-- Created : Fri Dec 8 1
4:05:32
2023
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
...
@@ -324,6 +324,12 @@ begin
...
@@ -324,6 +324,12 @@ begin
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
check_endianess_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
when
others
=>
-- prevent the slave from hanging the bus on invalid address
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
...
@@ -389,6 +395,7 @@ begin
...
@@ -389,6 +395,7 @@ begin
end
process
;
end
process
;
-- Check endianess register
rwaddr_reg
<=
wb_adr_i
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_err_o
<=
'0'
;
...
...
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @
874afe5c
...
@@ -243,4 +243,21 @@ peripheral {
...
@@ -243,4 +243,21 @@ peripheral {
};
};
reg {
name = "Check Endianess";
description = "Register showing the endianess";
prefix = "CHECK_ENDIANESS";
field {
name = "Check endianess register";
description = "Register for endianess. Holds a default value based on which the user \
can check anytime the endianess. Default is big endianess";
type = SLV;
size = 32;
access_dev= WRITE_ONLY;
access_bus=READ_ONLY;
};
};
};
};
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @
874afe5c
...
@@ -461,4 +461,8 @@ begin -- arch
...
@@ -461,4 +461,8 @@ begin -- arch
regs_in
.
sr_physical_uart_i
<=
'1'
when
g_WITH_PHYSICAL_UART
else
'0'
;
regs_in
.
sr_physical_uart_i
<=
'1'
when
g_WITH_PHYSICAL_UART
else
'0'
;
regs_in
.
sr_virtual_uart_i
<=
'1'
when
g_WITH_VIRTUAL_UART
else
'0'
;
regs_in
.
sr_virtual_uart_i
<=
'1'
when
g_WITH_VIRTUAL_UART
else
'0'
;
-- Register to check the endianess. Holds a default value and when user reads
-- it as it is, it means the endianess is big, else it is little
regs_in
.
check_endianess_i
<=
x"AABBCCDD"
;
end
arch
;
end
arch
;
testbench/wishbone/include/wb_uart_regs.vh
View file @
874afe5c
...
@@ -45,3 +45,4 @@
...
@@ -45,3 +45,4 @@
`define UART_CR_RX_FIFO_PURGE 32'h00000001
`define UART_CR_RX_FIFO_PURGE 32'h00000001
`define UART_CR_TX_FIFO_PURGE_OFFSET 1
`define UART_CR_TX_FIFO_PURGE_OFFSET 1
`define UART_CR_TX_FIFO_PURGE 32'h00000002
`define UART_CR_TX_FIFO_PURGE 32'h00000002
`define ADDR_UART_CHECK_ENDIANESS 5'h1c
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