altera: add missing gc_shiftreg

The recent merge lost our Altera work-alike.

altera: add missing gc_shiftreg
The recent merge lost our Altera work-alike.
81f2155b · Wesley W. Terpstra · 6fba1ad7 · 81f2155b · 81f2155b
Commit 81f2155b authored Aug 22, 2013 by Wesley W. Terpstra
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Manifest.py modules/genrams/altera/Manifest.py +2 -1

gc_shiftreg.vhd modules/genrams/altera/gc_shiftreg.vhd +38 -0

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--- a/modules/genrams/altera/Manifest.py
+++ b/modules/genrams/altera/Manifest.py
@@ -3,4 +3,5 @@ files = [
 "generic_simple_dpram.vhd",
 "generic_dpram.vhd",
 "generic_spram.vhd",
-"generic_sync_fifo.vhd"]
+"generic_sync_fifo.vhd",
+"gc_shiftreg.vhd"]
--- a/modules/genrams/altera/gc_shiftreg.vhd
+++ b/modules/genrams/altera/gc_shiftreg.vhd
+library ieee;
+
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.genram_pkg.all;
+
+entity gc_shiftreg is
+  generic (
+    g_size : integer);
+  port (
+    clk_i : in  std_logic;
+    en_i  : in  std_logic;
+    d_i   : in  std_logic;
+    q_o   : out std_logic;
+    a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+end gc_shiftreg;
+
+
+architecture rtl of gc_shiftreg is
+  signal a  : std_logic_vector(4 downto 0);
+  signal sr : std_logic_vector(g_size-1 downto 0);
+begin
+
+  a <= std_logic_vector(resize(unsigned(a_i), 5));
+  
+  p_srl : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if en_i = '1' then
+        sr <= sr(sr'left - 1 downto 0) & d_i;
+      end if;
+    end if;
+  end process;
+
+  q_o <= sr(TO_INTEGER(unsigned(a_i)));
+
+end rtl;