dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning),…

dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.

dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning),…
dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.
799c7394 · Nathan Pittet · fc5860ce · 799c7394
Commit 799c7394 authored Aug 02, 2022 by Nathan Pittet
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Showing with 4 additions and 5 deletions

gc_pi_regulator.vhd modules/dsp/gc_pi_regulator.vhd +4 -5

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--- a/modules/dsp/gc_pi_regulator.vhd
+++ b/modules/dsp/gc_pi_regulator.vhd
@@ -50,7 +50,7 @@ architecture rtl of gc_pi_regulator is
    x     :     signed;
    y     :     signed;
    o     : out signed;
-    limit : out std_logic) is
+    lim : out std_logic) is

    variable sum   : signed(o'length downto 0);

@@ -64,18 +64,17 @@ architecture rtl of gc_pi_regulator is

    if sum > v_max then
      o     := resize(v_max, o'length);
-      limit := '1';
+      lim := '1';
    elsif sum < v_min then
      o     := resize(v_min, o'length);
-      limit := '1';
+      lim := '1';
    else
      o     := sum(o'length-1 downto 0);
-      limit := '0';
+      lim := '0';
    end if;

  end f_clamp_add;

-  signal integ_limit_hit : std_logic;
  signal limit_sum1, limit_sum2 : std_logic;

 begin