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Platform-independent core collection
Commit 74e3dc6f authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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lm32: remove unused signals 

Some signals are flat-out unused
 => these are outright removed
Some signals are used only under certain conditions
 => these have the definitions made also conditional
parent 5eb407d8
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Showing with 99 additions and 272 deletions
modules/wishbone/wb_lm32/src/lm32_cpu.v
View file @ 74e3dc6f
......@@ -387,7 +387,6 @@ wire x_result_sel_sext_d; // Select X stage result from si
reg x_result_sel_sext_x;
`endif
wire x_result_sel_logic_d; // Select X stage result from logic op unit
reg x_result_sel_logic_x;
`ifdef CFG_USER_ENABLED
wire x_result_sel_user_d; // Select X stage result from user-defined logic
reg x_result_sel_user_x;
......@@ -447,16 +446,16 @@ reg scall_x;
wire eret_d; // Indicates an eret instruction
reg eret_x;
wire eret_q_x;
reg eret_m;
`ifdef CFG_TRACE_ENABLED
reg eret_m;
reg eret_w;
`endif
`ifdef CFG_DEBUG_ENABLED
wire bret_d; // Indicates a bret instruction
reg bret_x;
wire bret_q_x;
reg bret_m;
`ifdef CFG_TRACE_ENABLED
reg bret_m;
reg bret_w;
`endif
`endif
......@@ -540,7 +539,6 @@ reg rotate_x;
`endif
wire direction_d; // Which direction to shift in
reg direction_x;
reg direction_m;
wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
......@@ -2263,7 +2261,6 @@ begin
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext_x <= `FALSE;
`endif
x_result_sel_logic_x <= `FALSE;
`ifdef CFG_USER_ENABLED
x_result_sel_user_x <= `FALSE;
`endif
......@@ -2329,9 +2326,6 @@ begin
exception_m <= `FALSE;
load_m <= `FALSE;
store_m <= `FALSE;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction_m <= `FALSE;
`endif
write_enable_m <= `FALSE;
write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
condition_met_m <= `FALSE;
......@@ -2382,7 +2376,6 @@ begin
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext_x <= x_result_sel_sext_d;
`endif
x_result_sel_logic_x <= x_result_sel_logic_d;
`ifdef CFG_USER_ENABLED
x_result_sel_user_x <= x_result_sel_user_d;
`endif
......@@ -2455,9 +2448,6 @@ begin
`endif
end
m_bypass_enable_m <= m_bypass_enable_x;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction_m <= direction_x;
`endif
load_m <= load_x;
store_m <= store_x;
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
......@@ -2501,13 +2491,15 @@ begin
`endif
`ifdef CFG_TRACE_ENABLED
eid_m <= eid_x;
eret_m <= eret_q_x;
`endif
`ifdef CFG_DCACHE_ENABLED
dflush_m <= dflush_x;
`endif
eret_m <= eret_q_x;
`ifdef CFG_TRACE_ENABLED
`ifdef CFG_DEBUG_ENABLED
bret_m <= bret_q_x;
`endif
`endif
write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
`ifdef CFG_DEBUG_ENABLED
......
modules/wishbone/wb_lm32/src/lm32_decoder.v
View file @ 74e3dc6f
......@@ -359,7 +359,9 @@ wire op_sr;
wire op_sru;
wire op_sub;
wire op_sw;
`ifdef CFG_USER_ENABLED
wire op_user;
`endif
wire op_wcsr;
wire op_xnor;
wire op_xor;
......@@ -441,7 +443,9 @@ assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
`ifdef CFG_USER_ENABLED
assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
`endif
assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
......
modules/wishbone/wb_lm32/src/lm32_interrupt.v
View file @ 74e3dc6f
......@@ -108,9 +108,6 @@ reg [`LM32_WORD_RNG] csr_read_data;
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//p_ragma attribute asserted preserve_signal true
wire [interrupts-1:0] interrupt_n_exception;
wire [interrupts-1:0] ie_csr_read_data;
wire [interrupts-1:0] ip_csr_read_data;
wire [interrupts-1:0] im_csr_read_data;
// Interrupt CSRs
......@@ -135,17 +132,6 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted (active-low) or are already pending
assign asserted = ip | interrupt;
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
if (interrupts > 1)
begin
......
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