Testbench added for AXI cores

6b2c8891 · kblantos · 1621d6d1 · 6b2c8891 · 6b2c8891 · 6b2c8891
Commit 6b2c8891 authored Sep 07, 2022 by kblantos
14 changed files
--- a/testbench/axi/axi4lite32_axi4full64_bridge/Manifest.py
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/Manifest.py
+action="simulation"
+sim_tool="ghdl"
+target="generic"
+ghdl_opt="--std=08 -frelaxed-rules"
+sim_top="tb_axi4lite32_axi4full64_bridge"
+
+files="tb_axi4lite32_axi4full64_bridge.vhd"
+
+modules={"local" : ["../../../",
+                    "../../../modules/wishbone",
+                    "../../../modules/axi"]}
+
--- a/testbench/axi/axi4lite32_axi4full64_bridge/README.md
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/README.md
+This is a testbench in order to verify the behavior of the axi4lite 32-bits
+to axi4full 64-bits, bridge. Master is the axi4lite and the slave is axi4full.
+For the development of the RTL core and the testbench, the documentation that
+taken into account is : "AMBA AXI and ACE Protocol Specification". OSVVM used
+as verification methodology and GHDL is the simulator.
+
+NOTE: You can change the simulation time by changing the NOW variable in the stimulus
+
+The testing process is the following:
+  - Randomized inputs are given to the Design Under Test in order to check the functionality of the RTL core.
+  - FSM coverage. Legal and ilegal states are printed in the end.
+  - Assertions are used to check the functionality of the AXI4-Full and AXI4-Lite protocols
+
+How to run the test:
+
+  1) For this test you need to install HDLMAKE, GHDL and OSVVM(2020.05+)
+  2) Add in usr/local/lib/ghdl/vendors/config.sh the path of the OSVVM
+  3) Compile OSVVM by running the script: `/usr/local/lib/ghdl/vendors/compile-osvvm --all`
+  4) run hdlmake makefile
+  5) run make
+  6) run ./run.sh
+  7) (Optional) add in the run.sh --wave=waveform.ghw to see waveform with gtkwave
+  8) See the results of the test
+
--- a/testbench/axi/axi4lite32_axi4full64_bridge/run.sh
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/run.sh
+#!/bin/bash -e
+
+#This is a simple script to run simulations in GHDL
+
+TB=tb_axi4lite32_axi4full64_bridge
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM
+
--- a/testbench/axi/axi4lite32_axi4full64_bridge/tb_axi4lite32_axi4full64_bridge.vhd
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/tb_axi4lite32_axi4full64_bridge.vhd
--- a/testbench/axi/axi4lite_axi4full_bridge/Manifest.py
+++ b/testbench/axi/axi4lite_axi4full_bridge/Manifest.py
+action  ="simulation"
+sim_tool="ghdl"
+target  ="generic"
+ghdl_opt="--std=08 -frelaxed-rules"
+sim_top ="tb_axi4lite_axi4full_bridge"
+
+files ="tb_axi4lite_axi4full_bridge.vhd"
+
+modules = {"local" : ["../../../",]}
+
--- a/testbench/axi/axi4lite_axi4full_bridge/README.md
+++ b/testbench/axi/axi4lite_axi4full_bridge/README.md
+This is a testbench in order to verify the behavior of the axi4lite to axi4full
+bridge. Master is the axi4lite and the slave is axi4full.
+
+For the development of the RTL core and the testbench, the documentation that
+taken into account is : "AMBA AXI and ACE Protocol Specification". OSVVM used
+as verification methodology and GHDL is the simulator.
+
+NOTE: You can change the simulation time by changing the NOW variable in the stimulus
+      Also, add in the *run.sh* the --wave=waveform.ghw option in order to generate waveform
+      file through GHDL simulator.
+
+The testing process is the following:
+  - Randomized values are given to the Design Under Test input signals.
+  - FSM coverage. Legal and ilegal states are printed in the end of the simulation.
+  - Assertions are used to check the functionality of the AXI4-Full and AXI4-Lite protocols
+
+How to run the test:
+
+  1) For this test you need to install HDLMAKE, GHDL and OSVVM(2020.05+)
+  2) Add in usr/local/lib/ghdl/vendors/config.sh the path of the OSVVM
+  3) Compile OSVVM by running the script: `/usr/local/lib/ghdl/vendors/compile-osvvm --all`
+  4) run hdlmake makefile
+  5) run make
+  6) run ./run.sh
+  7) (Optional) add in the run.sh --wave=waveform.ghw to see waveform with gtkwave
+  8) See the results of the test
+
--- a/testbench/axi/axi4lite_axi4full_bridge/run.sh
+++ b/testbench/axi/axi4lite_axi4full_bridge/run.sh
+#!/bin/bash -e
+
+#This is a simple script to run simulations in GHDL
+
+TB=tb_axi4lite_axi4full_bridge
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM --wave=waveform.ghw
+
--- a/testbench/axi/axi4lite_axi4full_bridge/tb_axi4lite_axi4full_bridge.vhd
+++ b/testbench/axi/axi4lite_axi4full_bridge/tb_axi4lite_axi4full_bridge.vhd
--- a/testbench/axi/axi4lite_wb_bridge/Manifest.py
+++ b/testbench/axi/axi4lite_wb_bridge/Manifest.py
+action="simulation"
+sim_tool="ghdl"
+target="generic"
+ghdl_opt="--std=08 -frelaxed-rules"
+sim_top="tb_xaxi4lite_wb_bridge"
+
+files="tb_xaxi4lite_wb_bridge.vhd"
+modules={"local" : ["../../../",
+                    "../../../modules/wishbone",
+                    "../../../modules/axi"]}
+
--- a/testbench/axi/axi4lite_wb_bridge/README.md
+++ b/testbench/axi/axi4lite_wb_bridge/README.md
+This is the testbench for the axi4lite to wishbone bridge (axi4lite_wb_bridge).
+GHDL used as a simulator alongside with OSVVM methodology. The testing process is:
+
+  - Randomized inputs are given to the Design Under Test in order to check the 
+    functionality of the RTL core. 
+  - FSM coverage. Legal and ilegal state changes are printed in the end.
+  - Assertions are used to check that the protocols of AXI-Lite and Wishbone
+    behave as it is expected.
+
+How to run the test:
+  1) For this test you need to install HDLMAKE, GHDL and OSVVM(2020.05+)
+  2) Add in  `usr/local/lib/ghdl/vendors/config.sh` the path of the OSVVM
+  3) Compile OSVVM by running the script:
+      /usr/local/lib/ghdl/vendors/compile-osvvm --all
+  4) run `hdlmake makefile`
+  5) run `make`
+  6) run `./run.sh`
+  7) (Optional) add in the `run.sh` --wave=waveform.ghw to see waveform
+     with gtkwave
+  8) See the results of the test
--- a/testbench/axi/axi4lite_wb_bridge/run.sh
+++ b/testbench/axi/axi4lite_wb_bridge/run.sh
+#!/bin/bash -e
+
+#This is a simple script to run simulations in GHDL
+
+TB=tb_xaxi4lite_wb_bridge
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM --wave=waveform.ghw
+
+
--- a/testbench/axi/axi4lite_wb_bridge/tb_xaxi4lite_wb_bridge.vhd
+++ b/testbench/axi/axi4lite_wb_bridge/tb_xaxi4lite_wb_bridge.vhd
--- a/testbench/axi/z7_axi_gpio_expander/Manifest.py
+++ b/testbench/axi/z7_axi_gpio_expander/Manifest.py
-target = "xilinx"
-action = "simulation"
-sim_tool = "modelsim"
+target     = "xilinx"
+action     = "simulation"
+sim_tool   = "ghdl" #"modelsim"
 top_module = "sim_top_ps_gpio"
 syn_device = "XC7Z010"
+# This can be deleted when GHDL not used
+ghdl_opt = "--std=08 -frelaxed-rules"

 files = [ "gpio_axi.vhd", "sim_top_ps_gpio.vhd" ]


--- a/testbench/axi/z7_axi_gpio_expander/run.sh
+++ b/testbench/axi/z7_axi_gpio_expander/run.sh
+#!/bin/bash -e
+
+#This is a simple script to run simulations in GHDL
+
+TB=sim_top_ps_gpio
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB 
+echo "********************************************"