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Platform-independent core collection
Commit 6639f31a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wb_fine_pulse_gen: add missing rst_serdes input

parent 960a3e0b
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modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd
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...@@ -19,6 +19,7 @@ entity fine_pulse_gen_kintex7 is ...@@ -19,6 +19,7 @@ entity fine_pulse_gen_kintex7 is
clk_par_i : in std_logic; clk_par_i : in std_logic;
clk_serdes_i : in std_logic; clk_serdes_i : in std_logic;
rst_serdes_i : in std_logic;
rst_sys_n_i : in std_logic; rst_sys_n_i : in std_logic;
cont_i : in std_logic; cont_i : in std_logic;
...@@ -188,7 +189,7 @@ begin ...@@ -188,7 +189,7 @@ begin
OQ => dout_nodelay, OQ => dout_nodelay,
TBYTEIN => '0', TBYTEIN => '0',
TCE => '0', TCE => '0',
RST => rst); RST => rst_serdes_i);
gen_with_odelay : if g_use_odelay generate gen_with_odelay : if g_use_odelay generate
...@@ -211,7 +212,7 @@ begin ...@@ -211,7 +212,7 @@ begin
INC => '0', INC => '0',
ODATAIN => dout_predelay, ODATAIN => dout_predelay,
LD => odelay_load, LD => odelay_load,
REGRST => rst, REGRST => rst_serdes_i,
LDPIPEEN => '0', LDPIPEEN => '0',
CNTVALUEIN => odelay_ntaps, CNTVALUEIN => odelay_ntaps,
CINVCTRL => '0' CINVCTRL => '0'
......
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