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Platform-independent core collection
Commit 5e934bac authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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dsp: fixed sync (LO phase align) input in the I/Q (de)modulators

parent bd3892f8
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Showing with 12 additions and 7 deletions
modules/dsp/gc_iq_demodulator.vhd
View file @ 5e934bac
...@@ -26,6 +26,8 @@ entity gc_iq_demodulator is ...@@ -26,6 +26,8 @@ entity gc_iq_demodulator is
clk_i : in std_logic; clk_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
sync_p1_i : in std_logic;
-- ADC data input, 2's complement -- ADC data input, 2's complement
adc_data_i : in std_logic_vector(g_N-1 downto 0); adc_data_i : in std_logic_vector(g_N-1 downto 0);
...@@ -53,25 +55,28 @@ begin ...@@ -53,25 +55,28 @@ begin
state <= S_0; state <= S_0;
iacc <= (others => '0'); iacc <= (others => '0');
qacc <= (others => '0'); qacc <= (others => '0');
elsif sync_p1_i = '1' then
state <= S_PI2;
iacc <= resize(signed(adc_data_i), g_N + 1);
qacc <= (others => '0');
else else
case state is case state is
when S_0 => when S_0 =>
state <= S_PI2; state <= S_PI2;
iacc <= resize( signed( adc_data_i), g_N + 1); iacc <= resize(signed(adc_data_i), g_N + 1);
qacc <= (others => '0'); qacc <= (others => '0');
when S_PI2 => when S_PI2 =>
state <= S_PI; state <= S_PI;
iacc <= (others => '0'); iacc <= (others => '0');
qacc <= resize( signed(adc_data_i), g_N + 1); qacc <= resize(signed(adc_data_i), g_N + 1);
when S_PI => when S_PI =>
state <= S_3PI2; state <= S_3PI2;
iacc <= resize( -signed(adc_data_i), g_N + 1); iacc <= resize(-signed(adc_data_i), g_N + 1);
qacc <= (others => '0'); qacc <= (others => '0');
when S_3PI2 => when S_3PI2 =>
state <= S_0; state <= S_0;
iacc <= (others => '0'); iacc <= (others => '0');
qacc <= resize( -signed(adc_data_i), g_N + 1); qacc <= resize(-signed(adc_data_i), g_N + 1);
end case; end case;
end if; end if;
end if; end if;
......
modules/dsp/gc_iq_modulator.vhd
View file @ 5e934bac
...@@ -45,7 +45,7 @@ entity gc_iq_modulator is ...@@ -45,7 +45,7 @@ entity gc_iq_modulator is
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
en_i : in std_logic; en_i : in std_logic;
sync_i : in std_logic; sync_p1_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
i_i : in std_logic_vector(g_N-1 downto 0); i_i : in std_logic_vector(g_N-1 downto 0);
...@@ -74,7 +74,7 @@ begin ...@@ -74,7 +74,7 @@ begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
iin <= signed(i_i); iin <= signed(i_i);
qin <= signed(q_i); qin <= signed(q_i);
sync <= sync_i; sync <= sync_p1_i;
end if; end if;
end process; end process;
......
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