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Platform-independent core collection
Commit 52c113cd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana Committed by Tomasz Wlostowski
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Updated some documentation files 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Wlostowski's avatarTomasz Włostowski <tomasz.wlostowski@cern.ch>
parent b7786ef6
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x="297.63779"
y="311.81097"
id="text4293"
sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
sodipodi:role="line"
id="tspan4295"
x="297.63779"
y="311.81097">BIT 5</tspan><tspan
sodipodi:role="line"
x="297.63779"
y="324.31097"
id="tspan4297">- shift out SDA</tspan></text>
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style="opacity:0.98999999;fill:none;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
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sodipodi:linespacing="125%"
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xml:space="preserve"><tspan
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x="386.22049"
id="tspan4305"
sodipodi:role="line"
style="font-weight:bold">BIT 4</tspan><tspan
id="tspan4307"
y="324.31097"
x="386.22049"
sodipodi:role="line">- shift out SDA</tspan></text>
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sodipodi:linespacing="125%"
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xml:space="preserve"><tspan
y="311.81097"
x="474.80316"
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sodipodi:role="line"
style="font-weight:bold">BIT 3</tspan><tspan
id="tspan4317"
y="324.31097"
x="474.80316"
sodipodi:role="line">- shift out SDA</tspan></text>
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id="rect4319"
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sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
sodipodi:role="line"
id="tspan4323"
x="563.3858"
y="311.81097">BIT 2</tspan><tspan
sodipodi:role="line"
x="563.3858"
y="324.31097"
id="tspan4325">- shift out SDA</tspan></text>
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style="opacity:0.98999999;fill:none;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
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sodipodi:linespacing="125%"
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xml:space="preserve"><tspan
y="311.81097"
x="651.96844"
id="tspan4331"
sodipodi:role="line"
style="font-weight:bold">BIT 1</tspan><tspan
id="tspan4333"
y="324.31097"
x="651.96844"
sodipodi:role="line">- shift out SDA</tspan></text>
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xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
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sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
sodipodi:role="line"
id="tspan4339"
x="733.46454"
y="311.81097">BIT 0</tspan><tspan
sodipodi:role="line"
x="733.46454"
y="324.31097"
id="tspan4341">- shift out SDA</tspan><tspan
sodipodi:role="line"
x="733.46454"
y="336.81097"
id="tspan4355">- set w_done_p_o</tspan></text>
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width="92.125977"
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<path
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<path
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<path
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style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
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xml:space="preserve"
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sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
sodipodi:role="line"
id="tspan4270"
x="829.13391"
y="311.811">ACK BIT</tspan><tspan
sodipodi:role="line"
x="829.13391"
y="324.311"
id="tspan4272">- check ACK </tspan><tspan
id="tspan4357"
sodipodi:role="line"
x="829.13391"
y="336.811">from master</tspan></text>
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inkscape:connector-curvature="0"
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<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
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style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
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sodipodi:linespacing="125%"
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style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="216.14172"
x="793.70087"
id="tspan4365"
sodipodi:role="line"
style="font-weight:bold">ACK BIT</tspan><tspan
id="tspan4367"
y="228.64172"
x="793.70087"
sodipodi:role="line">- sample ACK </tspan><tspan
y="241.14172"
x="793.70087"
sodipodi:role="line"
id="tspan4369">from master</tspan></text>
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inkscape:connector-curvature="0"
id="path4371"
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sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
sodipodi:role="line"
id="tspan4375"
x="85.039368"
y="226.77165">BIT 7</tspan><tspan
sodipodi:role="line"
x="85.039368"
y="239.27165"
id="tspan4379">- bit_cnt++</tspan></text>
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<path
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<path
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xml:space="preserve"><tspan
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sodipodi:role="line"
style="font-weight:bold">BIT 6</tspan><tspan
id="tspan4475"
y="239.27165"
x="173.62204"
sodipodi:role="line">- bit_cnt++</tspan></text>
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sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
sodipodi:role="line"
id="tspan4481"
x="262.20471"
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sodipodi:role="line"
x="262.20471"
y="239.27165"
id="tspan4483">- bit_cnt++</tspan></text>
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id="text4487"
y="226.77165"
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sodipodi:role="line"
style="font-weight:bold">BIT 4</tspan><tspan
id="tspan4491"
y="239.27165"
x="350.78738"
sodipodi:role="line">- bit_cnt++</tspan></text>
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sodipodi:linespacing="125%"><tspan
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sodipodi:role="line"
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x="439.37009"
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sodipodi:role="line"
x="439.37009"
y="239.27165"
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id="text4503"
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sodipodi:role="line"
style="font-weight:bold">BIT 2</tspan><tspan
id="tspan4507"
y="239.27165"
x="527.95276"
sodipodi:role="line">- bit_cnt++</tspan></text>
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sodipodi:linespacing="125%"><tspan
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sodipodi:role="line"
id="tspan4513"
x="616.53546"
y="226.77165">BIT 1</tspan><tspan
sodipodi:role="line"
x="616.53546"
y="239.27165"
id="tspan4515">- bit_cnt++</tspan></text>
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......
doc/gc_i2c_slave/gc_i2c_slave.tex
View file @ 52c113cd
......@@ -88,7 +88,7 @@
\section{Introduction}
\label{sec:intro}
The \textit{i2c\_slave} VHDL module implements a simple I$^2$C
The \textit{gc\_i2c\_slave} VHDL module implements a simple I$^2$C
slave core capable of responding to I$^2$C transfers generated by a master. The module
is conceived to be controlled by an external module. Basic shifting of bits into the
module is handled during read transfers (from the slave's point of view), at the end of
......@@ -96,7 +96,7 @@ which the user is presented with the received byte. Similarly, in the case of a
transfer, the user inputs a byte to be sent, and the module handles shifting out of each
of the bits. The status of the module can be obtained via dedicated ports.
The main features of the \textit{i2c\_slave} module are:
The main features of the \textit{gc\_i2c\_slave} module are:
\begin{itemize}
\item simple operation
\begin{itemize}
......@@ -119,8 +119,8 @@ The main features of the \textit{i2c\_slave} module are:
\section{Instantiation}
\label{sec:instantiation}
This section offers information useful for instantiating the \textit{i2c\_slave} core module.
Table~\ref{tbl:ports} presents a list of ports of the \textit{i2c\_slave} module.
This section offers information useful for instantiating the \textit{gc\_i2c\_slave} core module.
Table~\ref{tbl:ports} presents a list of ports of the \textit{gc\_i2c\_slave} module.
I$^2$C-specific ports should be instantiated as outlined in Figure~\ref{fig:i2c-ports}, via
tri-state buffers enabled by the \textit{scl\_en\_o} lines \textit{sda\_en\_o}.
......@@ -157,42 +157,50 @@ To instantiate a tri-state buffer in VHDL:
\normalsize
The rest of the ports should be connected in a normal manner to an external controlling module. A
component declaration of the \textit{i2c\_slave} module is readily available in the
\textit{i2c\_slave\_pkg.vhd} package file. The package also defines constants for the
statuses readable at the \textit{stat\_o} pin. Refer to Section~\ref{sec:oper} for details
regarding the various statuses.
\begin{table}[h]
\caption{Ports of \textit{i2c\_slave} module}
\caption{Ports and generics of \textit{gc\_i2c\_slave} module}
\label{tbl:ports}
\centerline
{
\begin{tabular}{l c p{.65\textwidth}}
\begin{tabular}{l p{.8\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Name}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
clk\_i & 1 & Clock input \\
rst\_n\_i & 1 & Active-low reset input \\
scl\_i & 1 & SCL line input \\
scl\_o & 1 & SCL line output \\
scl\_en\_o & 1 & SCL line tri-state enable \\
sda\_i & 1 & SDA line input \\
sda\_o & 1 & SDA line output \\
sda\_en\_o & 1 & SDA line output tri-state enable \\
i2c\_addr\_i & 7 & I$^2$C slave address of the module, compaired against received address \\
ack\_n\_i & 1 & ACK to be sent to the master in case of master write transfers \\
op\_o & 1 & State of the R/W bit at the end of the address byte \\
tx\_byte\_i & 8 & Byte of data to be sent over I$^2$C \\
rx\_byte\_o & 8 & Byte received over I$^2$C \\
done\_p\_o & 1 & One \textit{clk\_i} cycle-wide pulse, signaling the slave module
has performed a valid transfer \\
stat\_o & 3 & Current state of communication \\
g\_gf\_len & Glitch filter length generic \newline
1 -- glitches narrower than 1 \textit{clk\_i} cycle are filtered \newline
2 -- glitches narrower than 2 \textit{clk\_i} cycles are filtered \newline
etc.\\
clk\_i & Clock input \\
rst\_n\_i & Active-low reset input \\
scl\_i & SCL line input \\
scl\_o & SCL line output \\
scl\_en\_o & SCL line tri-state enable \\
sda\_i & SDA line input \\
sda\_o & SDA line output \\
sda\_en\_o & SDA line output tri-state enable \\
i2c\_addr\_i & I$^2$C slave address of the module, compaired against received address \\
ack\_i & ACK to be sent to the master in case of master write transfers \newline
'1' -- send an ACK to the master (ACK bit = '0') \newline
'0' -- send an NACK to the master (NACK bit = '1') \\
tx\_byte\_i & Byte of data to be sent over I$^2$C \\
rx\_byte\_o & Byte received over I$^2$C \\
sta\_p\_o & Start condition on I$^2$C bus (one-cycle-wide pulse) \\
sto\_p\_o & Stop condition on I$^2$C bus (one-cycle-wide pulse) \\
addr\_good\_p\_o & Slave address received from master corresponds that on
i2c\_addr\_i (one-cycle-wide pulse) \\
r\_done\_p\_o & Slave read done (one-cycle-wide pulse) \\
w\_done\_p\_o & Slave write done (one-cycle-wide pulse) \\
op\_o & State of the R/W bit at the end of the address byte \\
\hline
\end{tabular}
}
\end{table}
\pagebreak
The rest of the ports should be connected in a normal manner to an external controlling module. A
component declaration of the \textit{gc\_i2c\_slave} module is readily available in the
\textit{gencores\_pkg.vhd} file.
%==============================================================================
% SEC: I2C bus
%==============================================================================
......@@ -227,7 +235,7 @@ A typical I$^2$C bit-level transfer (Figure~\ref{fig:i2c-bitlevel}) follows the
\end{itemize}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/i2c-bitlevel}}
\centerline{\includegraphics[width=.9\textwidth]{fig/i2c-bitlevel}}
\caption{Bit-level transfers on the I$^2$C bus}
\label{fig:i2c-bitlevel}
\end{figure}
......@@ -251,7 +259,7 @@ data transfer (Figure~\ref{fig:i2c-transf}):
\item the master ends data transfer by sending the stop condition
\end{itemize}
\begin{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/i2c-transf}}
\caption{Bytes transferred on the I$^2$C bus}
\label{fig:i2c-transf}
......@@ -264,101 +272,80 @@ data transfer (Figure~\ref{fig:i2c-transf}):
\section{Operation}
\label{sec:oper}
The \textit{i2c\_slave} waits for a start condition to be performed on the I$^2$C bus by a
The \textit{gc\_i2c\_slave} waits for a start condition to be performed on the I$^2$C bus by a
master module. The address is shifted in and if it matches the slave address set via
the \textit{i2c\_addr\_i} input, the \textit{done\_p\_o} output is set for one \textit{clk\_i}
cycle and the \textit{stat\_o} output signals an address match. Based on the eighth
bit of the first I2C transfer byte, the module then starts shifting in or out each byte
in the transfer, setting the \textit{done\_p\_o} output for one clock cycle after each
received/sent byte. The \textit{stat\_o} output can be checked to see if the byte has been
sent/received correctly.
When the cycle-wide \textit{done\_p\_o} output is high (after every successful transfer, or a
stop condition) the \textit{stat\_o} (possibly together with the \textit{op\_o}) output can be checked
to see the appropriate action to be taken. The various statuses possible at the
\textit{stat\_o} output are listed in Table~\ref{tbl:stat}.
the \textit{i2c\_addr\_i} input, the \textit{addr\_good\_p\_o} output is set for one
\textit{clk\_i} cycle Based on the eighth bit of the first I$^2$C transfer byte, the module
then starts shifting in or out each byte in the transfer, setting the the \textit{r\_done\_p\_o}
pin high for one \textit{clk\_i} cycle after each successfully read byte, and respectively
the \textit{w\_done\_p\_o} output after each successfully written byte.
\begin{table}[h]
\caption{Statuses at the \textit{stat\_o} pin}
\label{tbl:stat}
\centerline
{
\begin{tabular}{c p{.65\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{\textit{stat\_o}}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
00 & Slave idle, waiting for start condition. This is the state upon startup and after the I$^2$C stop
condition is received \\
01 & Address sent by the master matches that at \textit{i2c\_addr\_i}; \textit{op\_o}
valid \\
10 & Read done, waiting for ACK/NACK to send to master \\
11 & Write done, waiting for next byte to send to master \\
\hline
\end{tabular}
}
\end{table}
The \textit{ack\_i} port is used for sending the ACK to the master. The polarity of the bit
is opposite to that of the I$^2$C ACK signal. On the I$^2$C bus, a '0' signals an ACK while a '1'
an NACK. To send an ACK, the user sohuld input a '1' on the \textit{ack\_i} port.
Note that a '1' should be set at the input also when the address is ACKed, otherwise the slave
will not acknowledge its own address. NACKing the slave address can be used when the user
wants to isolate the slave from the bus.
The \textit{ack\_n\_i} port is used for sending the ACK to the master. The polarity of the bit
is that of the I$^2$C ACK signal ('0' -- ACK, '1' -- NACK). A '0' should be set
at the input also when the address is ACKed, otherwise the slave will not acknowledge its own
address. This implies that the \textit{ack\_n\_i} pin can be used to isolate the slave from the
bus.
Additionally, the slave module includes two one-cycle-wide pulse ports (\textit{sta\_p\_o} and
\textit{sto\_p\_o}), which signal when a start and stop condition occurs on the bus.
%------------------------------------------------------------------------------
\subsection{Read mode}
When the eighth bit of the address byte is low (R/W = '0'), the slave goes into read
mode. Each bit of the byte sent by the master is shifted in on the falling edge of SCL. After
eight bits have been shifted in, \textit{done\_p\_o} is set for one \textit{clk\_i} cycle and
the status signals a successful read ("10"). The received byte should be read from the
\textit{rx\_byte\_o} output and an ACK ('0') or NACK~('1') should be sent to the master via the
\textit{ack\_n\_i} pin. The \textit{i2c\_slave} module does not implement clock stretching,
so the \textit{ack\_n\_i} pin should be set before the SCL line goes high.
mode. Each bit of the byte sent by the master is shifted in on the rising edge of SCL. After
eight bits have been shifted in, \textit{r\_done\_p\_o} is set for one \textit{clk\_i}.
The received byte should be read from the \textit{rx\_byte\_o} output and an ACK~('1') or
NACK~('0') should be sent to the master via the \textit{ack\_i} pin. The \textit{gc\_i2c\_slave}
module does not implement clock stretching, so the \textit{ack\_i} pin should be set before
the SCL line goes high.
The steps below should be followed when reading one or more bytes sent by the master:
\begin{enumerate}
\item Wait for \textit{done\_p\_o} to go high, signaling the I$^2$C address of the slave
\item Wait for \textit{addr\_good\_p\_o} to go high, signaling the I$^2$C address of the slave
has been read.
\item Check that \textit{stat\_o} is "01" (address good) and that \textit{op\_o} is '0'
(master write, slave read). Set a '0' at the \textit{ack\_n\_i} input to send the
ACK to the address; if \textit{ack\_n\_i} is '1', the slave does not acknowledge its
own address.
\item Wait for \textit{done\_p\_o} to go high.
\item Check that \textit{stat\_o} is "10" (read done), read the received byte from
\textit{rx\_byte\_o} and write a '0' at \textit{ack\_n\_i} to send an ACK, or a
'1' to send an NACK.
\item Check that that \textit{op\_o} is '0' (master write, slave read). Set a '1' at the
\textit{ack\_i} input to send the ACK to the address; if \textit{ack\_i} is set '0', the slave
does not acknowledge its own address.
\item Wait for \textit{r\_done\_p\_o} to go high.
\item Read the received byte from \textit{rx\_byte\_o} and write a '1' at \textit{ack\_i}
to send an ACK, or a '0' to send an NACK.
\item The transfer is repeated until the master sends a stop condition.
\item After the stop condition is received, the \textit{done\_p\_o} goes high for one
clock cycle and the status is set to "00".
\item After the stop condition is received, \textit{sto\_p\_o} goes high for one \textit{clk\_i}
cycle and the slave goes idle.
\end{enumerate}
Note that on start conditions, \textit{sta\_p\_o} is set high for one \textit{clk\_i} cycle.
%------------------------------------------------------------------------------
\subsection{Write mode}
When a master reads from the slave, the eighth bit of the address byte is high
(R/W = '1'). In this case, the \textit{i2c\_slave} module goes in write mode, where
When the slave is to write to the master, the eighth bit of the address byte is high
(R/W = '1'). In this case, the \textit{gc\_i2c\_slave} module goes in write mode, where
the byte at the \textit{tx\_byte\_i} port is sent to the master. When the byte has been
successfully sent, the \textit{done\_p\_o} is high for one clock cycle and the \textit{stat\_o}
port has the value "11", signaling the slave has successfully sent a byte and is
awaiting the loading of another byte.
successfully sent, the \textit{w\_done\_p\_o} is high for one clock cycle, signaling the
slave has successfully sent a byte and is awaiting the loading of another byte.
The steps below should be followed when writing one or more bytes to a master:
\begin{enumerate}
\item Wait for \textit{done\_p\_o} to go high, signaling the I$^2$C address of the slave
\item Wait for \textit{addr\_good\_p\_o} to go high, signaling the I$^2$C address of the slave
has been read.
\item Check that \textit{stat\_o} is "01" (address good) and \textit{op\_o} is '1'
(master read, slave write). Set the byte to be sent to the master at the
\textit{tx\_byte\_i} input. Set a '0' at \textit{ack\_n\_i} to send the ACK to the address;
if \textit{ack\_n\_i} is '1', the slave does not acknowledge its own address.
\item Wait for \textit{done\_p\_o} to go high.
\item Check that \textit{stat\_o} is "11" (write done) and set the next byte to be
sent at the \textit{tx\_byte\_i} port.
\item Check that \textit{op\_o} is '1' (master read, slave write). Set the byte to be sent
to the master at the \textit{tx\_byte\_i} input. Set a '1' at \textit{ack\_i} to send the
ACK to the address; if \textit{ack\_i} is set '0', the slave does not acknowledge its own
address.
\item Wait for \textit{w\_done\_p\_o} to go high.
\item Set the next byte to be sent at the \textit{tx\_byte\_i} port.
\item If the master acknowledges the transfer, the next byte is sent, otherwise, the master
will send a stop condition, so the \textit{i2c\_slave} module is reset.
will send a stop condition, and the \textit{gc\_i2c\_slave} module is returned to IDLE. The
\textit{sto\_p\_o} output is also set high for one \textit{clk\_i} cycle.
\end{enumerate}
Note that if a stop condition is received from the master, the \textit{done\_p\_o} goes high for
one clock cycle and the status is set to "00".
Note that on start conditions, \textit{sta\_p\_o} is set high for one \textit{clk\_i} cycle.
%==============================================================================
% SEC: Implementation
......@@ -366,31 +353,44 @@ one clock cycle and the status is set to "00".
\section{Implementation}
\label{sec:implem}
This section presents implementation details of the \textit{i2c\_slave} module. A simplified
block diagram of the module is presented in Figure~\ref{fig:i2c-slave-bd}.
A simplified block diagram of the \textit{gc\_i2c\_slave} module is presented in
Figure~\ref{fig:i2c-slave-bd}. Deglitched versions of the SCL and SDA lines control
operation of the central finite-state machine (FSM), which sets the outputs and
controls the rest of the components in the module. The glitch filter lengths can
be set in units of \textit{clk\_i} cycles via the \textit{g\_gf\_len} module generic.
The FSM controls how outputs are set, when the reception and transmission shift registers
(RXSR/TXSR) are loaded and when they shift, and acknowledging to the address and bytes
sent by the master.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/i2c-slave-bd}}
\caption{Block diagram of \textit{i2c\_slave} module}
\caption{Block diagram of \textit{gc\_i2c\_slave} module}
\label{fig:i2c-slave-bd}
\end{figure}
Deglitched versions of the SCL and SDA lines control operation of the central finite-state
machine (FSM), which sets the outputs and controls the rest of the components in the module.
Figure~\ref{fig:fsm-diag} shows a simplified state transition diagram of the FSM,
and Table~\ref{tbl:fsm} lists the states of the FSM and the operations performed in each
state. Across the FSM, shifting of bits into the module is done on the rising edge
of SCL and shifting out is done on the falling edge of SCL. A three-bit counter is
used to count the number of received bits. This bit counter is incremented on the
rising edge of SCL. During read and write cycles, the FSM also changes states on
the SCL falling edge. A summary of the FSM actions with reference to the SCL line
on read and write transfer is shown in Figure~\ref{fig:fsm-and-scl}.
The FSM is sensitive to start and stop conditions and falling edges of the SCL line. It
controls how outputs are set, when the reception and transmission shift registers (RXSR/TXSR)
are loaded and when they shift, and acknowledging to the address and bytes sent by the
master. Table~\ref{tbl:fsm} lists the states of the FSM and the operations performed
in each state.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/fsm-diag}}
\caption{Simplified FSM state transition diagram}
\label{fig:fsm-diag}
\end{figure}
An internal watchdog counter is implemented inside the \textit{i2c\_slave} module. This counter
counts up to 1 second and is reset at the start of each state of the FSM. If the FSM stops
in one of the states because of a bus error, the watchdog resets the FSM, thereby stopping the
communication.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/fsm-and-scl}}
\caption{FSM actions on SCL edges}
\label{fig:fsm-and-scl}
\end{figure}
\begin{longtable}{l p{.7\textwidth}}
\caption{The states of the \textit{i2c\_slave} FSM}
\caption{The states of the \textit{gc\_i2c\_slave} FSM}
\label{tbl:fsm} \\
\hline
......@@ -406,73 +406,103 @@ communication.
\hline
\endfoot
\textit{IDLE} & Idle state, FSM default state after reset and the state returned to after
reception of a stop condition. \\
\textit{STA} & State reached after a start condition is received. On the falling edge
of SCL, the FSM transitions to \textit{ADDR} state. \\
\textit{ADDR} & Shift in 7 address bits and R/W bit and go to \textit{ADDR\_ACK}
state. Each bit is shifted in on the falling edge of SCL. If the
received address matches, \textit{op\_o} and \textit{done\_p\_o} are set. \\
\textit{ADDR\_ACK} & Check received address and send the ACK value at \textit{ack\_n\_i} if
the address corresponds to \textit{i2c\_addr\_i}. If the R/W bit is high,
go to \textit{RD} state, otherwise go to \textit{WR\_LOAD\_TXSR} state.
If received address does not match, NACK and go to \textit{IDLE}
state. \\
\textit{IDLE} & Default state after reset and the state returned to after
reception of a start and stop condition. \\
\textit{ADDR} & Shift in the address and R/W bit. \\
\textit{ADDR\_CHECK} & Check the address versus \textit{i2c\_addr\_i} and set the \textit{op\_o}
output as per the R/W bit. \\
\textit{ADDR\_ACK} & Send ACK depending on value of \textit{ack\_i} and go to \textit{RD} state
if the R/W bit is high, or to \textit{WR\_LOAD\_TXSR} state if R/W bit is low.
If \textit{ack\_i} is low, go back to \textit{IDLE}. \\
\textit{RD} & Shift in eight bits sent by master and go to \textit{RD\_ACK} state. Each bit
is shifted in on the falling edge of SCL. When eight bits have been shifted in,
set \textit{done\_p\_o}. \\
\textit{RD\_ACK} & Read \textit{ack\_n\_i} and forward it to \textit{sda\_o} (ACK/NACK
from external controller). If \textit{ack\_n\_i} is '0', then go back to
\textit{RD} state, else to \textit{IDLE} state. \\
\textit{WR\_LOAD\_TXSR} & Load TX shift register with data at \textit{tx\_byte\_i} input
is shifted in on the rising edge of SCL. \\
\textit{RD\_ACK} & Send ACK depending on value of \textit{ack\_i}. If \textit{ack\_i} is '1',
then go back to \textit{RD} state, else to \textit{IDLE} state. \\
\textit{WR\_LOAD\_TXSR} & Load TX shift register with data at \textit{tx\_byte\_i} input
and go to \textit{WR} state. \\
\textit{WR} & Shift out the eight bits of the TXSR starting with MSB and go to
\textit{WR\_ACK} state. TXSR shifts left on falling edge of SCL. When
eight bits have been shifted out, \textit{done\_p\_o} is set.\\
\textit{WR\_ACK} state. TXSR shifts left on each falling edge of SCL. \\
\textit{WR\_ACK} & Read ACK bit sent by master. If '0', go back to \textit{WR} state, otherwise
go to \textit{IDLE} state. \\
\end{longtable}
%------------------------------------------------------------------------------
\subsection{Output control}
To keep to the I$^2$C standard, the I$^2$C outputs (\textit{sda\_o}, \textit{scl\_o}) are
not directly driven high. Instead, they are driven low and their respective enable outputs
are driven high and low, to enable the output buffers. In fact, since no clock stretching
is implemented, the SCL line is always disabled.
Therefore, when the term "send" is used below, it means controlling the \textit{sda\_en\_o}
line high and low to enable the output buffer and send a '0', or leave the line high.
%------------------------------------------------------------------------------
\subsection{Address byte}
The transfer starts by the master sending a start condition on the I$^2$C bus.
The slave detects this start condition and starts shifting in the address bits while in the
\textit{ADDR} state. After the eighth bit has been shifted in, the FSM goes into the
\textit{ADDR\_CHECK} state, where it checks the received address versus the
\textit{i2c\_addr\_i} pin and if it matches, the FSM goes into the \textit{ADDR\_ACK} state,
where the slave waits for the \textit{ack\_i} input to be set by the external controller.
If the external controller sets the \textit{ack\_i} pin high while the slave is
in the \textit{ADDR\_ACK} state, the slave module acknowledges its address received
from the master, and the transfer continues as indicated by the eighth bit in the
address byte.
While in the \textit{ADDR\_CHECK} state, the \textit{op\_o} and \textit{addr\_good\_p\_o}
outputs are also set high (\textit{addr\_good\_p\_o} is set for one clock cycle and
\textit{op\_o} is set until the next I$^2$C transfer).
Important to note is that if the address received from the master does not correspond
to \textit{i2c\_addr\_i} when it is checked in the \textit{ADDR\_CHECK} state, the
slave module NACKs the transfer and goes back to the \textit{IDLE} state, setting an inhibit
signal. The purpose of this inhibit signal is to prevent the slave from reacting to
other bytes sent by a master to another slave on the I$^2$C bus. If this inhibit
signal were not present and if a byte sent by the master to another slave on the bus
matches the slave module's address at the \textit{i2c\_addr\_i} port, the slave module
would acknowledge this byte as its own address. The inhibit signal is cleared only when
receiving a start or a stop condition, as after one of these two, the master would
send the I$^2$C slave address again, and this is when the slave module should become
active again.
%------------------------------------------------------------------------------
\subsection{Reading from a master}
The slave will read from a master when this eighth bit is high ('1'). On read
transfers, the FSM is in the \textit{RD} state, where bits on the SDA line are shifted
in by the slave on the rising edge of SCL (see Figure~\ref{fig:fsm-and-scl}). This
happens until the eighth bit has been shifted in, at which point the \textit{r\_done\_p\_o}
pin is set for one clock cycle and the FSM goes into the \textit{RD\_ACK} state. Here,
the external module controls the \textit{ack\_i} pin to ACK/NACK the received byte,
as in the case of the \textit{ADDR\_ACK} state. If the external module ACKs the
transfer, the slave module goes back to the \textit{RD} state to read another byte
from the master, or to the \textit{IDLE} state otherwise.
%------------------------------------------------------------------------------
\subsection{Writing to a master}
The slave will write to a master when the eighth bit in the address byte is low ('0').
On write transfers, the FSM is in the \textit{WR} state, where bits on the SDA line
are shifted out of the slave on the falling edge of SCL (see Figure~\ref{fig:fsm-and-scl}).
This happens until the eight bit has been transferred, at which point the slave sents
the \textit{w\_done\_p\_o} pin for one clock cycle and it goes into the \textit{WR\_ACK}
state, where it waits for the master to acknowledge the sent byte. The ACK from the master
is sampled in on the rising edge of SCL and it is checked on the falling edge of SCL,
to determine whether a new write transfer should occur or not. If the master has
ACKed the transfer, the FSM goes back to the \textit{WR} state to send another byte to
the master, or to the \textit{IDLE} state otherwise.
%------------------------------------------------------------------------------
\subsection{Start and stop conditions on the bus}
A start or a stop condition will take the slave module back into the \textit{IDLE}
state, irrespective of other control signals internal to the module.
%\pagebreak
%\begin{table}[h]
% \caption{The states of the \textit{i2c\_slave} FSM}
% \label{tbl:fsm}
% \centerline
% {
% \begin{tabular}{l p{.7\textwidth}}
% \hline
% \multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\
% \hline
% \textit{IDLE} & Idle state, FSM default state after reset and the state returned to after
% reception of a stop condition. \\
% \textit{STA} & State reached after a start condition is received. On the falling edge
% of SCL, the FSM transitions to \textit{ADDR} state. \\
% \textit{ADDR} & Shift in 7 address bits and R/W bit and go to \textit{ADDR\_ACK}
% state. Each bit is shifted in on the falling edge of SCL. If the
% received address matches, \textit{op\_o} and \textit{done\_p\_o} are set. \\
% \textit{ADDR\_ACK} & Check received address and send the ACK value at \textit{ack\_n\_i} if
% the address corresponds to \textit{i2c\_addr\_i}. If the R/W bit is high,
% go to \textit{RD} state, otherwise go to \textit{WR\_LOAD\_TXSR} state.
% If received address does not match, NACK and go to \textit{IDLE}
% state. \\
% \textit{RD} & Shift in eight bits sent by master and go to \textit{RD\_ACK} state. Each bit
% is shifted in on the falling edge of SCL. When eight bits have been shifted in,
% set \textit{done\_p\_o}. \\
% \textit{RD\_ACK} & Read \textit{ack\_n\_i} and forward it to \textit{sda\_o} (ACK/NACK
% from external controller). If \textit{ack\_n\_i} is '0', then go back to
% \textit{RD} state, else to \textit{IDLE} state. \\
% \textit{WR\_LOAD\_TXSR} & Load TX shift register with data at \textit{tx\_byte\_i} input
% and go to \textit{WR} state. \\
% \textit{WR} & Shift out the eight bits of the TXSR starting with MSB and go to
% \textit{WR\_ACK} state. TXSR shifts left on falling edge of SCL. When
% eight bits have been shifted out, \textit{done\_p\_o} is set.\\
% \textit{WR\_ACK} & Read ACK bit sent by master. If '0', go back to \textit{WR} state, otherwise
% go to \textit{IDLE} state. \\
% \hline
% \end{tabular}
% }
%\end{table}
The inhibit signal is also cleared on these two conditions, as the master would
follow up by sending an address byte relevant to the slave module.
%==============================================================================
% Bibliography
......
doc/wb_i2c_bridge/cern-title.tex
View file @ 52c113cd
......@@ -5,11 +5,11 @@
%---------------------------------------------------------------
% title
%---------------------------------------------------------------
\noindent{\LARGE \textbf{VBCP to Wishbone bridge}}
\noindent{\LARGE \textbf{I$^2$C to Wishbone bridge}}
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\hfill 18 Dec. 2013
\vspace*{3cm}
......
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doc/wb_i2c_bridge/wb_i2c_bridge.tex
View file @ 52c113cd
......@@ -6,6 +6,9 @@
% Color package
\usepackage[usenames,dvipsnames]{color}
% Appendix package
\usepackage[toc,page]{appendix}
% Hyperrefs
\usepackage[
colorlinks = true,
......@@ -55,6 +58,7 @@
22-10-2013 & 0.03 & Added \textit{Access commands} section, updated document according to
changes in protocol \\
29-10-2013 & 0.04 & Changed PDF link colors \\
18-12-2013 & 1.00 & Finite version with watchdog timer and robust communication \\
\hline
\end{tabular}
}
......@@ -74,7 +78,7 @@
\section*{List of Abbreviations}
\begin{tabular}{l l}
FSM & Finite-State Machine \\
VBCP & Inter-Integrated Circuit (bus) \\
I$^2$C & Inter-Integrated Circuit (bus) \\
SysMon & ELMA crate System Monitor board \\
VME & VERSAmodule Eurocard \\
\end{tabular}
......@@ -89,23 +93,23 @@
\section{Introduction}
\label{sec:intro}
This document describes the \textit{vbcp\_wb} module, a VME Board Control Protocol (VBCP) to Wishbone
This document describes the \textit{wb\_i2c\_bridge} module, an I$^2$C to Wishbone
bridge HDL core for VME64x crates from ELMA. These crates offer the possibility of accessing
boards in VME slots via either VME, or VBCP. Boards not using the VME lines
on a slot can implement the \textit{vbcp\_wb} module on an FPGA; implements an
VBCP slave and translates VBCP accesses into Wishbone \cite{wb-spec} accesses to a
Wishbone slave device.
boards in VME slots via either VME, or I$^2$C. Boards not using the VME lines
on a slot can implement the \textit{wb\_i2c\_bridge} module on an FPGA. This module
implements an I$^2$C slave and translates I$^2$C accesses into Wishbone \cite{wb-spec}
accesses to a Wishbone slave device.
A typical system where the \textit{vbcp\_wb} module is employed is shown in
A typical system where the \textit{wb\_i2c\_bridge} module is employed is shown in
Figure~\ref{fig:sys}. ELMA VME crates contain a SysMon (system monitor) board~\cite{sysmon},
that is mainly used for monitoring VME voltages and controlling the fans of the VME crate.
The SysMon can be connected to via either a serial connection or Telnet. Then, sending
specific commands (see Section \ref{sec:testing}) via one of the two are translated by the
SysMon into VBCP accesses following the protocol described in Section~\ref{sec:vbcp}.
SysMon into I$^2$C accesses following the protocol described in Section~\ref{sec:elma-prot}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sys}}
\caption{Typical system for the \textit{vbcp\_wb} module}
\caption{Typical system for the \textit{wb\_i2c\_bridge} module}
\label{fig:sys}
\end{figure}
......@@ -115,13 +119,13 @@ SysMon into VBCP accesses following the protocol described in Section~\ref{sec:v
\section{Instantiation}
\label{sec:instantiation}
The ports of the \textit{vbcp\_wb} module are shown in Table~\ref{tbl:ports}.
The ports of the \textit{wb\_i2c\_bridge} module are shown in Table~\ref{tbl:ports}.
The I$^2$C signals should be connected to tri-state ports, as shown in
Figure~\ref{fig:i2c-ports}; Wishbone slaves should be connected to the
Wishbone master interface ports, prefixed with \textit{wbm}.
\begin{table}[h]
\caption{Ports of \textit{vbcp\_wb} module}
\begin{table}[hbtp]
\caption{Ports of \textit{wb\_i2c\_bridge} module}
\label{tbl:ports}
\centerline
{
......@@ -137,12 +141,14 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
scl\_en\_o & 1 & SCL line tri-state enable \\
scl\_i & 1 & SCL line input \\
scl\_o & 1 & SCL line output \\
i2c\_addr\_i & 7 & VBCP slave address on ELMA VBCP bus \\
i2c\_addr\_i & 7 & I$^2$C slave address on ELMA I$^2$C bus \\
tip\_o & 1 & Transfer In Progress \newline
'1' -- I$^2$C address sent by SysMon matches that of the VBCP slave \newline
'0' -- after transfer has completed and VBCP slave is idle \\
err\_o & 1 & Error bit, high for one \textit{clk\_i} cycle when the Wishbone address
'1' -- I$^2$C address sent by SysMon matches that of the I$^2$C slave \newline
'0' -- after transfer has completed and I$^2$C slave is idle \\
err\_p\_o & 1 & Error bit, high for one \textit{clk\_i} cycle when the Wishbone address
the SysMon tries to access is invalid \\
wdto\_p\_o & 1 & FSM watchdog timer time-out, high for one \textit{clk\_i} cycle when
the FSM watchdog has timed-out \\
wbm\_stb\_o & 1 & Wishbone data strobe output \\
wbm\_cyc\_o & 1 & Wishbone valid cycle output \\
wbm\_sel\_o & 4 & Wishbone byte select output \\
......@@ -160,12 +166,12 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
\begin{figure}[h]
\centerline{\includegraphics[width=.75\textwidth]{fig/i2c-ports}}
\caption{VBCP port external connections}
\caption{I$^2$C port external connections}
\label{fig:i2c-ports}
\end{figure}
%\begin{table}[h]
% \caption{Wishbone datasheet of \textit{vbcp\_wb} module}
% \caption{Wishbone datasheet of \textit{wb\_i2c\_bridge} module}
% \label{tbl:wb-ds}
% \centerline
% {
......@@ -173,7 +179,7 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
% \hline
% \multicolumn{1}{c}{\textbf{Description}} & \multicolumn{1}{c}{\textbf{Specification}} \\
% \hline
% General description & ELMA VBCP to Wishbone bridge \\
% General description & ELMA elma-prot to Wishbone bridge \\
% Supported cycles & Master, read/write \\
% Data port, size & 32-bit \\
% Data port, granularity & 32-bit \\
......@@ -201,21 +207,20 @@ Wishbone master interface ports, prefixed with \textit{wbm}.
%==============================================================================
% SEC: Testing
%==============================================================================
\section{Testing the \textit{vbcp\_wb} module}
\section{Testing the \textit{wb\_i2c\_bridge} module}
\label{sec:testing}
After proper synthesis and download to the FPGA, a Telnet or serial connection
should be made to the SysMon board. Commands can then be sent to the boards via
the SysMon. The two commands relevant for this basic test are \textit{readreg}
and \textit{writereg}. These and other commands relevant for accessing board
registers are outlined in Section~\ref{sec:vbcp-cmds}.
registers are outlined in Section~\ref{sec:elma-prot-cmds}.
The example below shows how to connect to an ELMA crate at IP address 1.2.3.4,
obtaining the value of a register at address 0x10 in a board in VME slot 2,
writing the hex value 0x1234 to the same register and reading it back to check for
proper modification.
\pagebreak
\begin{verbatim}
$ telnet 1.2.3.4
Trying 1.2.3.4...
......@@ -234,20 +239,18 @@ password:**********
%==============================================================================
% SEC: Protocol
%==============================================================================
\section{The VME Board Control Protocol}
\label{sec:vbcp}
\section{Data transfer protocol}
\label{sec:elma-prot}
%------------------------------------------------------------------------------
\subsection{Protocol details}
\label{sec:vbcp-prot}
\label{sec:elma-prot-prot}
The VME backplane provides two serial lines (\textit{SERCLK} and \textit{SERDAT})
on the P1 connector. These lines can be used to access boards placed in a VME
slots to control them, in cases where the VME interface is not implemented.
The VME Board Control Protocol (VBCP)~\cite{sysmon-i2c} has been defined for such
purposes. Using I$^2$C as a low-level protocol, the bytes of a register can be read
from or written to a VME board.
slot to control them, in cases where the VME interface is not implemented.
Using I$^2$C as a low-level protocol and the higher-level protocol defined here,
the bytes of a register can be read from or written to a VME board.
Figure~\ref{fig:sysmon-wr} shows a write operation from the SysMon to a VME
board. The process starts with the control byte, containing the board's
......@@ -280,15 +283,15 @@ are sent by the VME board in big-endian order.
%------------------------------------------------------------------------------
\subsection{Access commands}
\label{sec:vbcp-cmds}
\label{sec:elma-prot-cmds}
In order to send data to a VME board using VBCP, a user connects to the SysMon
via Telnet and sends commands which the SysMon translates into I$^2$C accesses
as outlined in the previous section. The commands supported by the \textit{vbcp\_wb}
module are shown in Table~\ref{tbl:cmds}.
In order to send data to a VME board, a user connects to the SysMon via Telnet
and sends commands which the SysMon translates into I$^2$C accesses as outlined
in the previous section. The commands Telnet commands to send to the SysMon are
shown in Table~\ref{tbl:cmds}.
\begin{table}[h]
\caption{The \textit{readreg} and \textit{writereg} commands}
\caption{SysMon Telnet commands for I$^2$C access}
\label{tbl:cmds}
\centerline
{
......@@ -301,7 +304,7 @@ module are shown in Table~\ref{tbl:cmds}.
writemregs \textit{slot addr v1 .. v8} & This command is similar to the \textit{writereg}
command, but it allows writing up to eight different values
to the same Wishbone register. The values are given in hexadecimal
format and are separate by spaces \\
format and are separated by spaces \\
readreg \textit{slot addr} & Returns the value of register at hex address \textit{addr} of
board in slot number \textit{slot} \\
\hline
......@@ -329,27 +332,31 @@ the VME board after every byte.
As Figure~\ref{fig:writemregs} shows, the data words are sent in little-endian order,
word 0 is sent first, followed by word 1 and so forth, until word 7.
\begin{figure}[h]
\centerline{\includegraphics[scale=.55]{fig/fsm}}
\caption{Main FSM of \textit{wb\_i2c\_bridge} module}
\label{fig:fsm}
\end{figure}
%==============================================================================
% SEC: Implem
%==============================================================================
\pagebreak
\section{Implementation}
\label{sec:implem}
In order to perform low-level I$^2$C transfers, the \textit{i2c\_slave} module
is instantiated and used within the \textit{vbcp\_wb}
module. The outputs of the \textit{i2c\_slave} module are used as controls
for an eight-state finite state machine (FSM), a simplified version of which
is shown in Figure~\ref{fig:fsm}. Table~\ref{tbl:fsm} also lists the states of
the state machine.
In order to perform low-level I$^2$C transfers, the \textit{gc\_i2c\_slave} module
is instantiated and used within the \textit{wb\_i2c\_bridge} module. The outputs
of the \textit{gc\_i2c\_slave} module are used as controls for an eight-state finite
state machine (FSM), a simplified version of which is shown in Figure~\ref{fig:fsm}.
Table~\ref{tbl:fsm} also lists the states of the FSM.
\begin{figure}[h]
\centerline{\includegraphics[scale=.65]{fig/fsm}}
\caption{Main FSM of \textit{vbcp\_wb} module}
\label{fig:fsm}
\end{figure}
Where the SysMon appears in the state names, it indicates what the SysMon action is.
For example, if the state of the FSM is \textit{SYSMON\_WR}, this means the SysMon
is writing and the \textit{wb\_i2c\_bridge} is reading.
\begin{table}[h]
\caption{States of \textit{vbcp\_wb} FSM}
\caption{States of \textit{wb\_i2c\_bridge} FSM}
\label{tbl:fsm}
\centerline
{
......@@ -357,80 +364,87 @@ the state machine.
\hline
\multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
IDLE & Wait for the \textit{i2c\_slave} module to receive the VBCP
address and go to \textit{WB\_ADR}. The starting value at the
\textit{op\_o} output of the \textit{i2c\_slave} module is stored
for checking in \textit{OPER} \\
WB\_ADR & Shift in the two address bytes sent via VBCP and go to
IDLE & Wait for the \textit{gc\_i2c\_slave} module to receive the I$^2$C
address and go to \textit{WB\_ADR} \\
WB\_ADR & Shift in the two address bytes sent via I$^2$C and go to
\textit{SIM\_WB\_TRANSF} \\
SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{OPER} if Wishbone address exists (Wishbone
\textit{ack} received), or \textit{IDLE} otherwise (Wishbone \textit{err}
received) \\
OPER & Check the \textit{op\_o} output of the \textit{i2c\_slave} module.
If different from the value at the start, go to \textit{SYSMON\_RD\_WB} state
(SysMon is reading from \textit{vbcp\_wb}), otherwise continue shifting
in bytes (SysMon writing to \textit{vbcp\_wb}) \\
OPER & Check the \textit{op\_o} output of the \textit{gc\_i2c\_slave} module.
If '1', go to \textit{SYSMON\_RD\_WB} state (SysMon is reading from
\textit{wb\_i2c\_bridge}), otherwise continue shifting in bytes (SysMon
writing to \textit{wb\_i2c\_bridge}) \\
SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{SYSMON\_WR\_WB}\\
SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
\textit{WB\_ADR} \\
SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in
\textit{WB\_ADR} and go to \textit{SYSMON\_RD} \\
SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{i2c\_slave}
SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{gc\_i2c\_slave}
module successfully finishes a write \\
\hline
\end{tabular}
}
\end{table}
When the \textit{i2c\_slave} module finishes a transfer (signaled by a \textit{done\_p\_o} pulse),
the status is checked and if it is as expected (e.g., \textit{address good} while in the
\textit{IDLE} state), the FSM advances to the next state. Where the SysMon appears in the state
names, it indicates what the SysMon action is. For example, if the state of the FSM is
\textit{SYSMON\_WR}, this means the SysMon is writing and the \textit{vbcp\_wb} is reading.
To better understand how the FSM operates, Figures \ref{fig:sysmon-wr-fsm} and
\ref{fig:sysmon-rd-fsm} can be consulted, where the state of the FSM is shown
during reads and writes from the SysMon.
When the SysMon writes (Figure~\ref{fig:sysmon-wr-fsm}), the
\textit{vbcp\_wb} module waits in the \textit{IDLE} state until
\textit{wb\_i2c\_bridge} module waits in the \textit{IDLE} state until
the I$^2$C address is received, then, while in the \textit{WB\_ADR} state,
it shifts in the Wishbone address. A Wishbone transfer is then simulated with
the received the address and if this address exists (a Wishbone \textit{ack}
is received), the first byte is shifted in while in the \textit{OPER} state,
followed by the next three bytes while in the \textit{SYSMON\_WR} state.
Finally, the register is written to in the \textit{SYSMON\_WR\_WB} state.
When the SysMon reads (Figure~\ref{fig:sysmon-rd-fsm}), the first few
steps are the same as for a read. The address is shifted in and
checked in the Wishbone transfer simulation state. In the case of a SysMon
reading from a board, however, the I$^2$C transfer is restarted and the order
is reversed (SysMon starts reading). Thus, while in \textit{OPER}, the FSM
detects a different value of \textit{op\_o} and goes into the
\textit{SYSMON\_RD\_WB} state. The value of the register is read while in this
state, and sent via VBCP in the \textit{SYSMON\_RD} state.
it shifts in the Wishbone address. A Wishbone simulation transfer is performed
from the received address. The simulation transfer is in fact a read transfer
from the address, but the data received from the register is not used in any way.
The purpose of this transfer is only to see if the received address exists, indicated
by a Wishbone \textit{ack} being received as a result of this transfer. If this
\textit{ack} is received, the first byte is shifted in while in the \textit{OPER}
state, followed by the next three bytes while in the \textit{SYSMON\_WR} state. The
register is written to in the \textit{SYSMON\_WR\_WB} state using a Wishbone write
transfer.
To allow for the \textit{writemregs} command, whereby up to eight registers can be
written with one I$^2$C transfer, the FSM goes back to the \textit{SYSMON\_WR} state
if the Wishbone write transfer completed successfully. The FSM will go back into the
\textit{IDLE} state when an I$^2$C stop condition is received, which is sent by
the SysMon after the \textit{writereg} or \textit{writemregs} has been completed.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-wr-fsm}}
\caption{FSM states when the SysMon writes to the \textit{vbcp\_wb}}
\caption{FSM states when the SysMon writes to the \textit{wb\_i2c\_bridge}}
\label{fig:sysmon-wr-fsm}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd-fsm}}
\caption{FSM states when the SysMon reads from the \textit{vbcp\_wb}}
\caption{FSM states when the SysMon reads from the \textit{wb\_i2c\_bridge}}
\label{fig:sysmon-rd-fsm}
\end{figure}
When the SysMon reads (Figure~\ref{fig:sysmon-rd-fsm}), the first few
steps are the same as for a write. The address is shifted in and checked in the
Wishbone transfer simulation state. In the case of a SysMon reading from a board,
however, the I$^2$C transfer is restarted and the order is reversed (SysMon starts
reading). Thus, while in \textit{OPER}, the FSM detects a high value on \textit{op\_o}
corresponding to an I$^2$C read transfer, and goes into the \textit{SYSMON\_RD\_WB}
state. The value of the register is read while in this state, and sent via I$^2$C
in the \textit{SYSMON\_RD} state.
The design also contains an FSM watchdog component, which resets the main FSM
in case of errors in communication. The watchdog timeout value is configured
via the \textit{g\_wdt\_max} generic and can be calculated as outlined in
Appendix~\ref{app:wdto-calc}.
%==============================================================================
% SEC: Synthesis results
%==============================================================================
\section{Synthesis results}
\label{sec:synth-res}
The synthesis results for the \textit{vbcp\_wb} design using \textit{xst}
The synthesis results for the \textit{wb\_i2c\_bridge} design using \textit{xst}
on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
\begin{table}[h]
......@@ -449,6 +463,47 @@ on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
}
\end{table}
%==============================================================================
% Appendix
%==============================================================================
\pagebreak
\begin{appendices}
\section{Watchdog timeout value calculation}
\label{app:wdto-calc}
In order to calculate the maximum watchdog timeout value, the following procedure
should be utilized.
First, the frequency on the I$^2$C communication in ELMA crates is 100~kHz. One
I$^2$C byte transfer always consists in 9 bits (eight bits for data plus one for
acknowledgement). Therefore, one I$^2$C byte is transferred within 90~$\mu$s.
To account for start and stop conditions and to allow for frequency changes on
the bus, one can consider one I$^2$C byte as 10 bits, therefore one I$^2$C
transfer can be considered to take 10~$\mu$s to complete.
Now, taking this into account and the period of the \textit{clk\_i} input,
$T_{clk\_i}$, the number of clock cycles needed to complete one I$^2$C byte transfer
can be calculated as:
\begin{equation}
N_{byte} = \frac{10 {\mu}s}{T_{clk\_i}}
\end{equation}
Within the ELMA crates, a maximum of 35 bytes can be sent through I$^2$C. This
happens when using the \textit{writemregs} command, where one byte is needed
for the I$^2$C address, two for the Wishbone address and a maximum of 32 bytes for
data (8 32-bit registers). Leaving a safety margin, one can calculate the
maximum watchdog timeout value to be the time needed to send 40 bytes via I$^2$C
on the bus:
\begin{equation}
g\_wdt\_max = 40 * N_{byte} = 40 * \frac{10 {\mu}s}{T_{clk\_i}}
\end{equation}
\end{appendices}
%==============================================================================
% Bibliography
%==============================================================================
......
doc/wb_xil_multiboot/fig/inst-clkcross.svg 0 → 100644
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doc/wb_xil_multiboot/wb_xil_multiboot.tex
View file @ 52c113cd
......@@ -58,6 +58,8 @@
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
28-10-2013 & 0.1 & First draft \\
18-12-2013 & 1.0 & Added WDTO bit to status register and information about the FSM watchdog
mechanism \\
\hline
\end{tabular}
}
......@@ -77,6 +79,7 @@
\section*{List of Abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
ICAP & Internal Configuration Access Port \\
IPROG & Internal PROGRAM\_B \\
OHWR & Open Hardware Repository \\
PROM & Programmable Read-Only Memory \\
......@@ -99,17 +102,18 @@ PROGRAM\_B) command to the configuration logic of the FPGA. This command trigger
deletion of the FPGA configuration and rewriting it with the new configuration
written to the PROM.
This document describes \textit{xil\_multiboot}, an Open Hardware (OHWR) \cite{ohwr}
This document describes \textit{wb\_xil\_multiboot}, an Open Hardware~\cite{ohwr}
FPGA design that can be used to remotely reprogram a Xilinx Spartan-6 FPGA using
MultiBoot technology.
MultiBoot technology. The core can be found within the \textit{general-cores}
library~\cite{gencores-ohwr} on OHWR.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/multiboot-bd}}
\label{fig:multiboot-bd}
\caption{Block diagram of \textit{xil\_multiboot} module}
\caption{Block diagram of \textit{wb\_xil\_multiboot} module}
\end{figure}
The main features of the \textit{xil\_multiboot} module are:
The main features of the \textit{wb\_xil\_multiboot} module are:
\begin{itemize}
\item software controls operation of the module
\begin{itemize}
......@@ -128,20 +132,20 @@ The main features of the \textit{xil\_multiboot} module are:
\end{itemize}
\end{itemize}
A block diagram of the \textit{xil\_multiboot} module is shown in Figure~\ref{fig:multiboot-bd}.
A block diagram of the \textit{wb\_xil\_multiboot} module is shown in Figure~\ref{fig:multiboot-bd}.
Users can write bitstream data to a flash by writing each byte of the bitstream to a module register
(in the \textit{multiboot\_regs}) module. Writing to the flash is done via the \textit{spi\_master}
module under the control of the finite-state machine (FSM) module (\textit{multiboot\_fsm}). After the
bitstream has been written to the flash module, a remote reprogramming command is sent
to the configuration logic by setting a bit in one of the control registers. The
Xilinx \textit{ICAP\_SPARTAN6} primitive is the interface between the \textit{xil\_multiboot}
Xilinx \textit{ICAP\_SPARTAN6} primitive is the interface between the \textit{wb\_xil\_multiboot}
module and the FPGA configuration logic.
For the rest of the document, the external PROM chip that the FPGA uses to
program itself will be referred to as flash, since a flash chip was used
as the external PROM during the design of the module. However, this does not
mean \textit{xil\_multiboot} works only with flash chips. Any 8-bit SPI PROM
should be usable with the \textit{xil\_multiboot} design.
mean \textit{wb\_xil\_multiboot} works only with flash chips. Any 8-bit SPI PROM
should be usable with the \textit{wb\_xil\_multiboot} design.
%==============================================================================
% SEC: Instantiation
......@@ -149,7 +153,7 @@ should be usable with the \textit{xil\_multiboot} design.
\section{Instantiation}
\label{sec:instantiation}
Table~\ref{tbl:ports} lists the ports of the \textit{xil\_multiboot} module.
Table~\ref{tbl:ports} lists the ports of the \textit{wb\_xil\_multiboot} module.
In order to instantiate the MultiBoot module, one needs to connect
the Wishbone slave ports to a Wishbone master, such as the \textit{xwb\_crossbar}
Wishbone crossbar module on OHWR \cite{gencores-ohwr}. The SPI ports should be
......@@ -164,7 +168,7 @@ connected directly to the FPGA output ports connected to the flash chip.
\hline
\multicolumn{1}{c}{\textbf{Port}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
clk\_i & 1 & Clock input \\
clk\_i & 1 & Clock input (max. 20~MHz) \\
rst\_n\_i & 1 & Active-low reset input \\
wbs\_i & & Wishbone slave interface inputs \\
wbs\_o & & Wishbone slave interface outputs \\
......@@ -182,6 +186,18 @@ library~\cite{gencores-ohwr} needs to be imported into the design. This library
the structures for the Wishbone slave interface ports (\textit{wbs\_i} and \textit{wbs\_o})
are defined.
Further note that the maximum \textit{clk\_i} frequency allowable is 20~MHz, due
to constraints of the ICAP component from Xilinx. Should a greater system clock
frequency be used in the design, the user can instantiate the \textit{wb\_xil\_multiboot}
module using a \textit{wb\_clock\_crossing} component from the OHWR \textit{general-cores}
library~\cite{gencores-ohwr}. This is shown in Figure~\ref{fig:inst-clkcross}.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/inst-clkcross}}
\caption{Instantiation when the system clock is greater than 20~MHz}
\label{fig:inst-clkcross}
\end{figure}
%==============================================================================
% SEC: Using
%==============================================================================
......@@ -190,10 +206,9 @@ are defined.
\label{sec:instantiation}
For an example project of where the Xilinx MultiBoot module is used, see the
CONV-TTL-BLO project~\cite{ctb-proj}. The firmware of this project, starting from
version 2.0, instantiates the MultiBoot module. The project also contains example
Python scripts for writing a bitstream to the flash. Refer to the project
webpage~\cite{ctb-proj} for more information.
CONV-TTL-BLO project~\cite{ctb-proj}. The firmware of this projectuses the MultiBoot
module. The project also contains example Python scripts for writing a bitstream to
the flash. Refer to the project webpage~\cite{ctb-proj} for more information.
Table~\ref{tbl:workflow} shows the MultiBoot workflow~\cite{xtp059}. See \cite{gen-bitstream}
for pointers on how to generate a MultiBoot bitstream. The address map of the MultiBoot module
......@@ -216,7 +231,7 @@ user should write as part of the MultiBoot workflow.
op-code into the MBBAR register \\
\rownumber & Write the Golden bitstream start address and flash chip read command
op-code into the GBBAR register \\
\rownumber & Unlock the IPROG bit in the FPGA by setting CR.IPROG\_UNL \\
\rownumber & Unlock the IPROG bit in the FPGA by setting CR.IPROG\_UNLOCK \\
\rownumber & Issue a reprogramming command to the FPGA by setting CR.IPROG \\
\hline
\end{tabular}
......@@ -352,13 +367,13 @@ bitstreams for a MultiBoot design.
%------------------------------------------------------------------------------
\subsection{Important note regarding MultiBoot bitstreams}
Users should be aware that they should include the \textit{xil\_multiboot} module
Users should be aware that they should include the \textit{wb\_xil\_multiboot} module
when generating a new MultiBoot bitsream. Otherwise, once a bitstream without
the \textit{xil\_multiboot} module inside it is loaded into the FPGA, the
the \textit{wb\_xil\_multiboot} module inside it is loaded into the FPGA, the
remote reprogramming capability of the FPGA is lost, and the user will need
to use JTAG or other means to program the FPGA with a MultiBoot-enabled design.
Thus, always remember to include the \textit{xil\_multiboot} module in any bitstream
Thus, always remember to include the \textit{wb\_xil\_multiboot} module in any bitstream
generated after the Golden bitstream.
%==============================================================================
......@@ -369,23 +384,13 @@ generated after the Golden bitstream.
A block diagram of the design has already been presented in
Figure~\ref{fig:multiboot-bd}. This section describes the actions of the sub-modules
in the \textit{xil\_multiboot} module. The description is rather high-level,
in the \textit{wb\_xil\_multiboot} module. The description is rather high-level,
some details are omitted for ease of understanding. The main purpose of this
section is for the reader to understand how the MultiBoot module works together with
the flash chip and the configuration logic to achieve FPGA reprogramming, rather
than specifying every detail about the module and its sub-modules.
For more involved details, the user is free to consult the code in the project
repository~\cite{ctb-repo}.
The \textit{multiboot\_fsm} module is at the heart of the design. It implements
a finite-state machine (FSM) with 34 states, which controls operation of the module.
A simplified diagram of the FSM is shown in Figure~\ref{fig:fsm}. The diagram shows the various
phases the FSM is in, and Table~\ref{tbl:fsm} lists these phases. Bear in mind
that each phase may contain multiple FSM states. However, many of these states
are just steps of accessing configuration logic through the Xilinx ICAP module,
so for simplicity they are not listed in this manual. Refer to the code for
more complete description.
than specifying every detail about the module and its sub-modules. For more involved
details, the user is free to consult the code in the project
repository~\cite{gencores-ohwr}.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/fsm}}
......@@ -416,6 +421,15 @@ more complete description.
}
\end{table}
The \textit{multiboot\_fsm} module is at the heart of the design. It implements
a finite-state machine (FSM) with 34 states, which controls operation of the module.
A simplified diagram of the FSM is shown in Figure~\ref{fig:fsm}. The diagram shows the various
phases the FSM is in, and Table~\ref{tbl:fsm} lists these phases. Bear in mind
that each phase may contain multiple FSM states. However, many of these states
are just steps of accessing configuration logic through the Xilinx ICAP module,
so for simplicity they are not listed in this manual. Refer to the code for
more complete description.
%------------------------------------------------------------------------------
\subsection{Sending data to the flash chip}
\label{sec:implem-spi}
......@@ -504,13 +518,13 @@ The Spartan-6 FPGA contains registers which can be read to get the stauts of the
configuration logic. In order to read these registers, a special sequence must be
followed. The sequece (listed in Table 6-1 of~\cite{ug380}) is implemented in the
\textit{multiboot\_fsm}. Table~\ref{tbl:rdcfgreg-seq} lists the sequence users
should follow to read out an FPGA configuration register via the \textit{xil\_multiboot}
should follow to read out an FPGA configuration register via the \textit{wb\_xil\_multiboot}
module.
\setcounter{rownr}{0}
\begin{table}[h]
\caption{Configuration register readout via \textit{xil\_multiboot}}
\caption{Configuration register readout via \textit{wb\_xil\_multiboot}}
\label{tbl:rdcfgreg-seq}
\centerline {
\begin{tabular}{c p{.7\textwidth}}
......@@ -532,7 +546,7 @@ module.
}
\end{table}
When the user sets the RDCFGREG bit in the \textit{xil\_multiboot} control register (CR),
When the user sets the RDCFGREG bit in the \textit{wb\_xil\_multiboot} control register (CR),
the \textit{multiboot\_fsm} initiates the configuration register readout sequence.
It first sends a synchronization word, and then takes the value of CFGREGADR from
the CR and use it to build a Type 1 configuration frame to read the configuration
......@@ -543,14 +557,14 @@ continues to perform the final steps of the configuration register readout seque
prior to returning to IDLE.
Note that some configuration registers in the Spartan-6 FPGA are more than 16 bits wide.
The \textit{xil\_multiboot} module does not support reading the full length of the
The \textit{wb\_xil\_multiboot} module does not support reading the full length of the
registers; it can only return the least significant 16 bits of the registers.
%------------------------------------------------------------------------------
\subsection{Sending the IPROG command}
Table~\ref{tbl:iprog} lists the actions needed to issue the IPROG command to the
FPGA using the \textit{xil\_multiboot} module. When the IPROG bit is set in the CR,
FPGA using the \textit{wb\_xil\_multiboot} module. When the IPROG bit is set in the CR,
the \textit{multiboot\_fsm} handles sending the IPROG sequence (Table 7-1,
p.130~\cite{ug380}) to the ICAP.
......@@ -587,13 +601,29 @@ an IPROG succeeds. This version number can be stored into a read-only register i
FPGA and read after the IPROG command. An example of this is given in the CONV-TTL-BLO
project~\cite{ctb-proj}.
%------------------------------------------------------------------------------
\subsection{FSM watchdog timer}
An FSM watchdog timer component (\textit{gc\_fsm\_watchdog} on OHWR) is instantiated
in the design. This component is used to reset the main FSM in case an error
occurs and the FSM stalls waiting for an action. The timeout value of the
watchdog timer is set to 512, since it was established from the component's
simulation that the phase of the FSM that would take the longest number of
cycles to complete (the SPI phase) would complete and return to IDLE
within 218 clock cycles. A safe value of 512 was selected to allow some tolerance
to the FSM, while making sure that it would return to its IDLE state in
case of errors.
When the FSM watchdog fires, the SR.WDTO bit is set. This bit can be cleared by
writing a '1' to it.
%==============================================================================
% SEC: Modifying
%==============================================================================
\section{Modifying the design}
\label{sec:modify}
The \textit{xil\_multiboot} module is purposely modular in case users want to
The \textit{wb\_xil\_multiboot} module is purposely modular in case users want to
interface to different FPGA interconnect standards, or different flash chips.
In order to make modifications to the design, knowledge of VHDL is required.
......@@ -610,13 +640,13 @@ the steps to be followed are listed in Table~\ref{tbl:ch-intercon}.
\hline
\textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\
\hline
\rownumber & Change \textit{wbs\_i} and \textit{wbs\_o} in \textit{xil\_multiboot}
\rownumber & Change \textit{wbs\_i} and \textit{wbs\_o} in \textit{wb\_xil\_multiboot}
ports to the preferred interconnect ports \\
\rownumber & Implement or change the current \textit{multiboot\_regs}
module, keeping the interface to the FSM side (e.g., the
\textit{multiboot\_cr\_iprog\_o} port, etc.) \\
\rownumber & Instantiate the new \textit{multiboot\_regs} module into the
\textit{xil\_multiboot} module \\
\textit{wb\_xil\_multiboot} module \\
\hline
\end{tabular}
}
......@@ -649,7 +679,7 @@ performed in case these SPI settings need to be changed.
Another potential addition to the design would be the capability of reading
the full value of all FPGA configuration registers. As outlined in
Section~\ref{sec:implem-rdcfgreg}, some configuration registers are more than
16 bits in length, and the \textit{xil\_multiboot} module cannot return their full
16 bits in length, and the \textit{wb\_xil\_multiboot} module cannot return their full
value. This can be modified by, implementing an extra COUNT field in the CR;
the \textit{multiboot\_fsm} can then use this field to build a Type 1 configuration
package to return the full length of the configuration register. More information
......@@ -661,7 +691,7 @@ on this can be found in the Configuration Packets section of~\cite{ug380}.
\section{Synthesis results}
\label{sec:synth-res}
The synthesis results for the \textit{xil\_multiboot} design using \textit{xst}
The synthesis results for the \textit{wb\_xil\_multiboot} design using \textit{xst}
on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
\begin{table}[h]
......@@ -716,7 +746,7 @@ sections detail the fields of each register.
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..18 & \textit{Reserved} & -- & X & \\
17 & IPROG & R/W & 0 & IPROG bit \\
16 & IPROG\_UNL & R/W & 0 & IPROG unlock bit \\
16 & IPROG\_UNLOCK & R/W & 0 & IPROG unlock bit \\
15..7 & \textit{Reserved} & -- & X & \\
6 & RDCFGREG & R/W & 0 & Read config register \\
5..0 & CFGREGADR & R/W & 0 & Config register address \\
......@@ -731,7 +761,7 @@ sections detail the fields of each register.
\textit{Reserved} & Write as '0'; read undefined \\
IPROG & When 1, it triggers the FSM to send the IPROG command to the ICAP controller \newline
This bit needs to be unlocked by setting the IPROG\_UNL bit in a previous cycle \\
IPROG\_UNL & Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing
IPROG\_UNLOCK & Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing
the IPROG bit \\
RDCFGREG & Initiate a read from the FPGA configuration register at address CFGREGADR \newline
This bit is automatically cleared by hardware \\
......@@ -741,13 +771,14 @@ sections detail the fields of each register.
}
%------------------------------------------------------------------------------
\subsection{IMGR -- Image Register}
\label{app:imgr}
\subsection{SR -- Status Register}
\label{app:sr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..17 & \textit{Reserved} & -- & X & \\
16 & VALID & R/O & 0 & Image register is valid \\
31..18 & \textit{Reserved} & -- & X & \\
17 & WDTO & R/W & 0 & FSM watchdog timeout \\
16 & IMGVALID & R/O & 0 & Image register is valid \\
15..0 & CFGREGIMG & R/O & 0 & Config. register image \\
\end{tabular}
......@@ -759,7 +790,9 @@ sections detail the fields of each register.
\textbf{Field} & \textbf{Description} \\
\textit{Reserved} & Write as '0'; read undefined \\
VALID & A read has been performed from the FPGA configuration
WDTO & The FSM watchdog timer has timed out and reset the main FSM \newline
This bit can be cleared by writing a '1' to it \\
IMGVALID & A read has been performed from the FPGA configuration
register at address CR.CFGREGADR, and its value is
present in CFGREGIMG \\
CFGREGIMG & Contains the value of the FPGA configuration register;
......
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