Skip to content

P
Platform-independent core collection
Commit 526683f6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

wb_uart: increase RX FIFO count register width to 16 bits to cater for large FIFOs

parent 768dbac1
Hide whitespace changes
Inline Side-by-side
Showing with 9 additions and 13 deletions
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @ 526683f6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug 25 17:17:50 2020
-- Created : Fri Oct 16 13:22:41 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -28,7 +28,7 @@ package uart_wbgen2_pkg is
sr_tx_fifo_empty_i : std_logic;
sr_tx_fifo_full_i : std_logic;
sr_rx_fifo_overflow_i : std_logic;
sr_rx_fifo_bytes_i : std_logic_vector(7 downto 0);
sr_rx_fifo_bytes_i : std_logic_vector(15 downto 0);
rdr_rx_data_i : std_logic_vector(7 downto 0);
host_tdr_rdy_i : std_logic;
host_rdr_data_i : std_logic_vector(7 downto 0);
......
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ 526683f6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_wb.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug 25 17:17:50 2020
-- Created : Fri Oct 16 13:22:41 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -111,15 +111,7 @@ begin
rddata_reg(5) <= regs_i.sr_tx_fifo_empty_i;
rddata_reg(6) <= regs_i.sr_tx_fifo_full_i;
rddata_reg(7) <= regs_i.sr_rx_fifo_overflow_i;
rddata_reg(15 downto 8) <= regs_i.sr_rx_fifo_bytes_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(23 downto 8) <= regs_i.sr_rx_fifo_bytes_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @ 526683f6
......@@ -98,7 +98,7 @@ peripheral {
prefix = "RX_FIFO_BYTES";
type = SLV;
size = 8;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 526683f6
......@@ -276,6 +276,10 @@ begin -- arch
regs_in.sr_tx_fifo_full_i <= tx_fifo_full;
regs_in.sr_tx_fifo_empty_i <= tx_fifo_empty;
regs_in.sr_rx_fifo_bytes_i (rx_fifo_count'length-1 downto 0) <= rx_fifo_count;
regs_in.sr_rx_fifo_bytes_i ( 15 downto rx_fifo_count'length ) <= (others => '0');
phys_tx_start <= '1' when tx_fifo_state = IDLE and tx_fifo_empty = '0' else '0';
p_rx_fifo_overflow : process(clk_sys_i)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment