Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
P
Platform-independent core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
18
Issues
18
List
Board
Labels
Milestones
Merge Requests
5
Merge Requests
5
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Platform-independent core collection
Commits
4e0bee16
Commit
4e0bee16
authored
Nov 27, 2018
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
sim: import onewire simulation model from opencores project
parent
def3aa71
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
115 additions
and
0 deletions
+115
-0
onewire_slave_model.v
sim/onewire_slave_model.v
+115
-0
No files found.
sim/onewire_slave_model.v
0 → 100644
View file @
4e0bee16
//////////////////////////////////////////////////////////////////////////////
// //
// 1-wire (owr) slave model //
// //
// Copyright (C) 2010 Iztok Jeras //
// //
//////////////////////////////////////////////////////////////////////////////
// //
// This HDL is free hardware: you can redistribute it and/or modify //
// it under the terms of the GNU Lesser General Public License //
// as published by the Free Software Foundation, either //
// version 3 of the License, or (at your option) any later version. //
// //
// This RTL is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
//////////////////////////////////////////////////////////////////////////////
`timescale
1u
s
/
1
ns
module
onewire_slave_model
#(
// time slot (min=15.0, typ=30.0, max=60.0)
parameter
TS
=
30.0
)(
// configuration
input
wire
ena
,
// response enable
input
wire
ovd
,
// overdrive mode select
input
wire
dat_r
,
// read data
output
wire
dat_w
,
// write data
// 1-wire
inout
wire
owr
)
;
// IO
reg
pul
;
reg
dat
;
// events
event
sample_dat
;
event
sample_rst
;
//////////////////////////////////////////////////////////////////////////////
// IO
//////////////////////////////////////////////////////////////////////////////
// onewire open collector signal
assign
owr
=
pul
&
ena
?
1'b0
:
1'bz
;
// read data output
assign
dat_w
=
ena
?
dat
:
1'bz
;
//////////////////////////////////////////////////////////////////////////////
// events inside a cycle
//////////////////////////////////////////////////////////////////////////////
// power up state
initial
pul
<=
1'b0
;
always
@
(
negedge
owr
)
if
(
ena
)
transfer
(
ovd
,
dat_r
,
dat
)
;
task
automatic
transfer
(
input
ovd
,
input
dat_r
,
output
dat_w
)
;
begin
// provide read data response
pul
=
~
dat_r
;
// wait 1 time slot
if
(
ovd
)
#(
1
*
TS
/
8
)
;
else
#(
1
*
TS
)
;
// write data is sampled here
->
sample_dat
;
dat_w
=
owr
;
// release the wire
pul
=
1'b0
;
// fork into data or reset cycle
fork
// transfer data
begin
:
transfer_dat
// if cycle ends before reset is detected
if
(
~
owr
)
@
(
posedge
owr
)
;
// disable reset path
disable
transfer_rst
;
end
// transfer reset
begin
:
transfer_rst
// wait 7 time slots
if
(
ovd
)
#(
7
*
TS
/
8
)
;
else
#(
7
*
TS
)
;
// reset is sampled here
->
sample_rst
;
// if reset is detected disable data path
if
(
~
owr
)
disable
transfer_dat
;
// wait for reset low to end
@
(
posedge
owr
)
// wait 1 time slot
if
(
ovd
)
#(
1
*
TS
/
8
)
;
else
#(
1
*
TS
)
;
// provide presence pulse
pul
=
1'b1
;
// wait 4 time slot
if
(
ovd
)
#(
4
*
TS
/
8
)
;
else
#(
4
*
TS
)
;
// release the wire
pul
=
1'b0
;
end
join
end
endtask
endmodule
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment