Fix response signalling in AXI4Lite-to-WB bridge wrapper

The response should not be EXOKAY unless an atomic access is requested by the master using the LOCK signals. This bridge does not even support atomic accesses (it's an AXI4-Lite slave and does not have the LOCK signals) so it's required to respond OKAY even if the master does attempt an atomic access (this is how the master knows that the slave does not support atomic accesses). The AXI4-Lite specification clearly states that the EXOKAY response is not supported in AXI4-Lite.

Fix response signalling in AXI4Lite-to-WB bridge wrapper
The response should not be EXOKAY unless an atomic access is requested by the master using the LOCK signals. This bridge does not even support atomic accesses (it's an AXI4-Lite slave and does not have the LOCK signals) so it's required to respond OKAY even if the master does attempt an atomic access (this is how the master knows that the slave does not support atomic accesses). The AXI4-Lite specification clearly states that the EXOKAY response is not supported in AXI4-Lite.
392ed83d · Marcus Comstedt · Olof Kindgren · 971c2e77 · 392ed83d
Commit 392ed83d authored Apr 23, 2020 by Marcus Comstedt Committed by Olof Kindgren Apr 30, 2020
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xwb_axi4lite_bridge.vhd modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd +4 -4

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--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -113,7 +113,7 @@ begin
              wb_master_o.stb <= '0';
              if(wb_master_i.ack = '1') then
                state <= IDLE;
-                axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+                axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
                axi4_slave_o.RDATA <= wb_master_i.dat;
                axi4_slave_o.RVALID <= '1';
                axi4_slave_o.RLAST <= '1';
@@ -130,7 +130,7 @@ begin
              wb_master_o.stb <= '0';
              if(wb_master_i.ack = '1') then
                state <= RESPONSE_WRITE;
-                axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+                axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
                wb_master_o.cyc    <= '0';
              else
                state <= WAIT_ACK_WRITE;
@@ -142,7 +142,7 @@ begin
          when WAIT_ACK_WRITE =>
            if(wb_master_i.ack = '1') then
              state              <= RESPONSE_WRITE;
-              axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+              axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
              wb_master_o.cyc    <= '0';
            elsif count = c_timeout then
              state              <= RESPONSE_WRITE;
@@ -154,7 +154,7 @@ begin
          when WAIT_ACK_READ =>
            if(wb_master_i.ack = '1') then
              state              <= IDLE;
-              axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+              axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
              axi4_slave_o.RVALID <= '1';
              axi4_slave_o.RLAST <= '1';
              axi4_slave_o.RDATA <= wb_master_i.dat;