Commit 3051df4c authored by kblantos's avatar kblantos

Final update to README in AXI/ tests

parent 66de3f0f
## Description ## Description
This is a testbench in order to verify the behavior of the axi4lite 32-bits to axi4full 64-bits, bridge [axi4lite32_axi4full64_bridge](../../modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd). Master is the axi4lite and the slave is axi4full. Testbench for [axi4lite32_axi4full64_bridge](../../modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd) which is a bridge from AXI4Lite32 to AXI4Full64. Master is the axi4lite and the slave is axi4full.
NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument to this script: NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument to this script:
```console ```console
......
## Description ## Description
This is a testbench in order to verify the behavior of the axi4lite to axi4full bridge [axi4lite_axi4full_bridge](../../modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd). Master is the axi4lite and the slave is axi4full. Testbench for [axi4lite_axi4full_bridge](../../modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd) which is a bridge from AXI4Lite to AXI4Full. Master is the axi4lite and the slave is axi4full.
NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument (integer) to this script: NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument (integer) to this script:
```console ```console
......
## Description ## Description
This is the testbench for the AXI4 Lite to Wishbone bridge core [axi4lite_wb_bridge](../../modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd). Testbench for [axi4lite_wb_bridge](../../modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd) which is a bridge from AXI4 Lite to Wishbone. In this core, the Master is AXI4 Lite and Slave is Wishbone.
In this core, the Master is AXI4 Lite and Slave is Wishbone.
NOTE: By default, the simulation time is 4ms. To change this, run the test and pass the simulation time as an argument (integer) to this script: NOTE: By default, the simulation time is 4ms. To change this, run the test and pass the simulation time as an argument (integer) to this script:
```console ```console
......
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