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Platform-independent core collection
Commit 213132e6 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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all: Regenerate Wishbone interfaces

parent fce11846
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Showing with 233 additions and 220 deletions
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @ 213132e6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Oct 4 18:46:41 2011
-- Created : Thu Feb 14 10:36:11 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -60,6 +60,7 @@ package uart_wbgen2_pkg is
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body uart_wbgen2_pkg is
......@@ -71,16 +72,28 @@ else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
variable tmp: t_uart_in_registers;
begin
tmp.sr_tx_busy_i := left.sr_tx_busy_i or right.sr_tx_busy_i;
tmp.sr_rx_rdy_i := left.sr_rx_rdy_i or right.sr_rx_rdy_i;
tmp.rdr_rx_data_i := left.rdr_rx_data_i or right.rdr_rx_data_i;
tmp.host_tdr_rdy_i := left.host_tdr_rdy_i or right.host_tdr_rdy_i;
tmp.host_rdr_data_i := left.host_rdr_data_i or right.host_rdr_data_i;
tmp.host_rdr_rdy_i := left.host_rdr_rdy_i or right.host_rdr_rdy_i;
tmp.host_rdr_count_i := left.host_rdr_count_i or right.host_rdr_count_i;
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
end function;
end package body;
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ 213132e6
This diff is collapsed.
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 213132e6
......@@ -99,19 +99,21 @@ architecture syn of wb_simple_uart is
component simple_uart_wb
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers);
regs_o : out t_uart_out_registers
);
end component;
signal rx_ready_reg : std_logic;
......@@ -174,16 +176,17 @@ begin -- syn
U_WB_SLAVE : simple_uart_wb
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(2 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
rdr_rack_o => rdr_rack,
host_rack_o => host_rack,
......
modules/wishbone/wb_vic/wb_slave_vic.vhd
View file @ 213132e6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_slave_vic.vhd
-- Author : auto-generated by wbgen2 from wb_slave_vic.wb
-- Created : Thu Sep 27 16:06:58 2012
-- Created : Thu Feb 14 10:35:14 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_vic.wb
......
modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
View file @ 213132e6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : xloader_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from xloader_wb.wb
-- Created : Thu Jun 21 15:17:30 2012
-- Created : Thu Feb 14 10:33:37 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xloader_wb.wb
......
modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
View file @ 213132e6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : xloader_wb.vhd
-- Author : auto-generated by wbgen2 from xloader_wb.wb
-- Created : Thu Jun 21 15:17:30 2012
-- Created : Thu Feb 14 10:33:37 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xloader_wb.wb
......@@ -118,13 +118,13 @@ begin
xldr_csr_exit_int <= wrdata_reg(6);
xldr_csr_clkdiv_int <= wrdata_reg(13 downto 8);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.csr_done_i;
rddata_reg(2) <= regs_i.csr_error_i;
rddata_reg(3) <= regs_i.csr_busy_i;
rddata_reg(4) <= xldr_csr_msbf_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(5) <= '0';
rddata_reg(6) <= '0';
rddata_reg(13 downto 8) <= xldr_csr_clkdiv_int;
rddata_reg(7) <= 'X';
rddata_reg(14) <= 'X';
......
sim/regs/xloader_regs.vh
View file @ 213132e6
`define ADDR_XLDR_CSR 4'h0
`define ADDR_XLDR_CSR 5'h0
`define XLDR_CSR_START_OFFSET 0
`define XLDR_CSR_START 32'h00000001
`define XLDR_CSR_DONE_OFFSET 1
......@@ -11,20 +11,27 @@
`define XLDR_CSR_MSBF 32'h00000010
`define XLDR_CSR_SWRST_OFFSET 5
`define XLDR_CSR_SWRST 32'h00000020
`define XLDR_CSR_EXIT_OFFSET 6
`define XLDR_CSR_EXIT 32'h00000040
`define XLDR_CSR_CLKDIV_OFFSET 8
`define XLDR_CSR_CLKDIV 32'h00003f00
`define ADDR_XLDR_FIFO_R0 4'h4
`define ADDR_XLDR_BTRIGR 5'h4
`define ADDR_XLDR_GPIOR 5'h8
`define ADDR_XLDR_IDR 5'hc
`define ADDR_XLDR_FIFO_R0 5'h10
`define XLDR_FIFO_R0_XSIZE_OFFSET 0
`define XLDR_FIFO_R0_XSIZE 32'h00000003
`define XLDR_FIFO_R0_XLAST_OFFSET 2
`define XLDR_FIFO_R0_XLAST 32'h00000004
`define ADDR_XLDR_FIFO_R1 4'h8
`define ADDR_XLDR_FIFO_R1 5'h14
`define XLDR_FIFO_R1_XDATA_OFFSET 0
`define XLDR_FIFO_R1_XDATA 32'hffffffff
`define ADDR_XLDR_FIFO_CSR 4'hc
`define ADDR_XLDR_FIFO_CSR 5'h18
`define XLDR_FIFO_CSR_FULL_OFFSET 16
`define XLDR_FIFO_CSR_FULL 32'h00010000
`define XLDR_FIFO_CSR_EMPTY_OFFSET 17
`define XLDR_FIFO_CSR_EMPTY 32'h00020000
`define XLDR_FIFO_CSR_CLEAR_BUS_OFFSET 18
`define XLDR_FIFO_CSR_CLEAR_BUS 32'h00040000
`define XLDR_FIFO_CSR_USEDW_OFFSET 0
`define XLDR_FIFO_CSR_USEDW 32'h000000ff
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