Merge remote-tracking branch 'origin/eva-ds182x' into tom-proposed-master-feb27

Conflicts: modules/common/gencores_pkg.vhd

Merge remote-tracking branch 'origin/eva-ds182x' into tom-proposed-master-feb27
Conflicts: modules/common/gencores_pkg.vhd
1c2dd12b · Tomasz Wlostowski · c03ea2cf · 49afba43 · 1c2dd12b · 1c2dd12b
Commit 1c2dd12b authored Feb 28, 2017 by Tomasz Wlostowski
4 changed files
--- a/modules/common/gc_ds182x_interface.vhd
+++ b/modules/common/gc_ds182x_interface.vhd
--- a/modules/common/gc_dyn_extend_pulse.vhd
+++ b/modules/common/gc_dyn_extend_pulse.vhd
+-------------------------------------------------------------------------------
+-- Title      : Pulse width extender
+-- Project    : General Cores library
+-------------------------------------------------------------------------------
+-- File       : gc_extend_pulse.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2009-09-01
+-- Last update: 2012-06-19
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Synchronous pulse extender. Generates a pulse of programmable width upon
+-- detection of a rising edge in the input.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-09-01  0.9      twlostow        Created
+-- 2011-04-18  1.0      twlostow        Added comments & header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+
+entity gc_dyn_extend_pulse is
+  generic
+    (
+      -- Number of bits of the  len_i input
+      g_len_width : natural := 10
+      );
+  port (
+    clk_i      : in  std_logic;
+    rst_n_i    : in  std_logic;
+    -- input pulse (synchronous to clk_i)
+    pulse_i    : in  std_logic;
+    -- output pulse length in clk_i cycles
+    len_i      : in std_logic_vector(g_len_width-1 downto 0);
+    -- extended output pulse
+    extended_o : out std_logic := '0');
+end gc_dyn_extend_pulse;
+
+architecture rtl of gc_dyn_extend_pulse is
+
+  signal cntr : unsigned(g_len_width-1 downto 0);
+  signal extended_int : std_logic;
+  
+begin  -- rtl
+
+  extend : process (clk_i, rst_n_i)
+  begin  -- process extend
+    if rst_n_i = '0' then                   -- asynchronous reset (active low)
+      extended_int <= '0';
+      cntr       <= (others => '0');
+    elsif clk_i'event and clk_i = '1' then  -- rising clock edge
+      if(pulse_i = '1') then
+        extended_int <= '1';
+        cntr       <= unsigned(len_i) - 2;
+      elsif cntr /= to_unsigned(0, cntr'length) then
+        cntr <= cntr - 1;
+      else
+        extended_int <= '0';
+      end if;
+    end if;
+  end process extend;
+
+  extended_o <= pulse_i or extended_int;
+
+end rtl;
+
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -6,6 +6,7 @@
 -- Author     : Tomasz Wlostowski
 --              Theodor-Adrian Stana
 --              Matthieu Cattin
+--              Evangelia Gousiou
 --              Dimitrios Lampridis
 -- Company    : CERN
 -- Created    : 2009-09-01
@@ -37,6 +38,15 @@
 -- from http://www.gnu.org/licenses/lgpl-2.1.html
 --
 -------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2009-09-01  0.9      twlostow        Created
+-- 2011-04-18  1.0      twlostow        Added comments & header
+-- 2013-11-20  1.1      tstana          Added glitch filter and I2C slave
+-- 2014-03-14  1.2      mcattin         Added dynamic glitch filter
+-- 2014-03-20  1.3      mcattin         Added bicolor led controller
+-- 2016-09-26  1.4      egousiou        Added one-wire DS182x interface
+-------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;
@@ -63,6 +73,17 @@ package gencores_pkg is
      extended_o : out std_logic);
  end component;

+  component gc_dyn_extend_pulse is
+    generic (
+      g_len_width : natural := 10);
+  port (
+    clk_i      : in  std_logic;
+    rst_n_i    : in  std_logic;
+    pulse_i    : in  std_logic;
+    len_i      : in std_logic_vector(g_len_width-1 downto 0);
+    extended_o : out std_logic := '0');
+  end component;
+
  ------------------------------------------------------------------------------
  -- CRC generator
  ------------------------------------------------------------------------------
@@ -262,6 +283,7 @@ package gencores_pkg is
    );
  end component;

+
  ------------------------------------------------------------------------------
  -- Round robin arbiter
  ------------------------------------------------------------------------------
@@ -328,8 +350,7 @@ package gencores_pkg is
        -- 0 - SCL and SDA lines are passed only through synchronizer
        -- 1 - one clk_i glitches filtered
        -- 2 - two clk_i glitches filtered
-        g_gf_len        : natural := 0;
-        g_auto_addr_ack : boolean := FALSE
+        g_gf_len : natural := 0
        );
    port
      (
@@ -504,6 +525,50 @@ package gencores_pkg is
      signals_pN_o                 : out std_logic_vector(g_signal_num-1 downto 0));
  end component;

+
+  ------------------------------------------------------------------------------
+  -- Priority encoder
+  ------------------------------------------------------------------------------  
+  component gc_prio_encoder is
+  generic (
+    g_width : integer);
+  port (
+    d_i     : in  std_logic_vector(g_width-1 downto 0);
+    therm_o : out std_logic_vector(g_width-1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- Delay generator
+  ------------------------------------------------------------------------------
+  component gc_delay_gen is
+  generic(
+    g_delay_cycles : in natural;
+    g_data_width   : in natural);
+
+  port(clk_i   : in  std_logic;  
+       rst_n_i : in  std_logic;  
+       d_i     : in  std_logic_vector(g_data_width - 1 downto 0);
+       q_o     : out std_logic_vector(g_data_width - 1 downto 0));
+  end component;
+
+  ------------------------------------------------------------------------------
+  -- One-wire interface to DS1820 and DS1822
+  ------------------------------------------------------------------------------  
+  component gc_ds182x_interface is
+  generic
+    (freq      : integer := 40);
+  port
+    (clk_i     : in    std_logic;
+     rst_n_i   : in    std_logic;
+     pps_p_i   : in    std_logic;
+     onewire_b : inout std_logic;
+     id_o      : out   std_logic_vector(63 downto 0);
+     temper_o  : out   std_logic_vector(15 downto 0);
+     id_read_o : out   std_logic;
+     id_ok_o   : out   std_logic);
+  end component;
+
+
  --============================================================================
  -- Procedures and functions
  --============================================================================
@@ -517,7 +582,6 @@ package gencores_pkg is
  function f_gray_encode(x   : std_logic_vector) return std_logic_vector;
  function f_gray_decode(x   : std_logic_vector; step : natural) return std_logic_vector;
  function log2_ceil(N       : natural) return positive;
-
  function f_bool2int (b : boolean) return natural;
  function f_int2bool (n : natural) return boolean;

@@ -633,6 +697,7 @@ package body gencores_pkg is
    end if;
  end;

+
  ------------------------------------------------------------------------------
  -- Converts a boolean to natural integer (false -> 0, true -> 1)
  ------------------------------------------------------------------------------
@@ -657,4 +722,5 @@ package body gencores_pkg is
    end if;
  end;

+
 end gencores_pkg;
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -1144,7 +1144,7 @@ package wishbone_pkg is
    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000000ff",
+      addr_last   => x"000000000000ffff",
      product     => (
        vendor_id => x"000000000000CE42",  -- CERN
        device_id => x"ffffffff",