Commit 08b8f29f authored by Nathan Pittet's avatar Nathan Pittet Committed by Tomasz Wlostowski

dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning),…

dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.
parent cdaab29e
...@@ -50,7 +50,7 @@ architecture rtl of gc_pi_regulator is ...@@ -50,7 +50,7 @@ architecture rtl of gc_pi_regulator is
x : signed; x : signed;
y : signed; y : signed;
o : out signed; o : out signed;
limit : out std_logic) is lim : out std_logic) is
variable sum : signed(o'length downto 0); variable sum : signed(o'length downto 0);
...@@ -64,18 +64,17 @@ architecture rtl of gc_pi_regulator is ...@@ -64,18 +64,17 @@ architecture rtl of gc_pi_regulator is
if sum > v_max then if sum > v_max then
o := resize(v_max, o'length); o := resize(v_max, o'length);
limit := '1'; lim := '1';
elsif sum < v_min then elsif sum < v_min then
o := resize(v_min, o'length); o := resize(v_min, o'length);
limit := '1'; lim := '1';
else else
o := sum(o'length-1 downto 0); o := sum(o'length-1 downto 0);
limit := '0'; lim := '0';
end if; end if;
end f_clamp_add; end f_clamp_add;
signal integ_limit_hit : std_logic;
signal limit_sum1, limit_sum2 : std_logic; signal limit_sum1, limit_sum2 : std_logic;
begin begin
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment