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Created with Raphaël 2.2.015Jul111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar28f_string2svl: accept any bound for string parameter.wishbone_pkg: remove unused variable.Mention wb_metadata and add it to the Manifest.Add wb_metadata module.virtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1wr-switch-sw-v6.0wr-switch-sw-v6.0Move gc_ds182x_readout to a subdir, add README.Move gc_ds182x_readout.vhd to a subdirectory.Add wb_ds182x_readoutAdd gc_sync_word_wr in Manifest.wb_vic.vhd: minor refactoring.wb_slave_adapter: add default values for input ports.wishbone.md: add a diagram.common: include gc_dec_8b10b in gencores packagesimulation: make ghdl happywishbone_pkg.vhd: removed merge artifactswrpc-v4.2_gsi_a10wrpc-v4.2_gsi_a10merged wrpc-v4.2_gsi into a10 developmentManifest: fixed build flow for arria2 phywrpc-v4.2_gsiwrpc-v4.2_gsiManifest (common): added matrix_pkg.vhdwishbone_pkg: cleaned up f_sdb_auto_device and f_sdb_auto_device functionswb_pcie: converted arria2 ip to quartus 18.1modified wb_pcie bridge has working white rabbitwishbone_pkg: cherry-picked f_sdb_embed_device overloadwb_uart: code cleanupwb_uart: tie unused signals to zero when not using virtual UARTwb_pcie: converted arria2 ip to quartus 18.1gsi_master_a10gsi_master_a10common: added module that can count inc/dec pulses in different clk domainsgenrams: conditionally generate CDC synchronisers for async_fifos.common: reset cleanup for gc_frequency_meterMerge branch 'master' into proposed_mastercommon: added module that can count inc/dec pulses in different clk domainsFixed-latency-s…Fixed-latency-streamersgenrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written togenrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written tovirtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1greg-fifogreg-fifoREADME: document wishbone modules.gc_sync_word_wr.vhd: add comments.README: document rams and fifos (WIP)Manifest: fix axi package namemodules/common: add gc_comparator to packageMerge branch 'greg-axi' into proposed_mastermove axi-wb bridge to dedicated dir for AXI