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Created with Raphaël 2.2.07Sep110Aug83229Jul282520181628Jun2231May1222Mar1325Feb1711310Jan16Dec26Oct130Sep292823Aug929Jul11May615Apr11Mar17Feb161221Jan181512617Dec1611922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216Minor fixes in some Common CoresTestbench added for Common core. Makefile and .yml file added to run CI for Gateware SimulationsTestbench added for genram coresTestbench added for wishbone coresTestbench added for AXI coresaxi: add axi4lite_axi4full_bridgewb_fine_pulse_gen: declare IDELAYCTRL component locallyaxi4_pkg: added missing AxPROT fields + fixed WSTRB lengthaxi4_pkg: increase address with to 64 bitsdsp/gc_cordic: move testbench to use Logger/UnitTest codesim: start redesign/cleanup of the SystemVerilog testing code:axi4_pkg: declare AXI4 burst type constantsdsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.npittet-pi-reg-…npittet-pi-reg-changesdsp/gc_pi_regulator: synthesis fails when g_INTEGRATOR_BITS is bigger than 32 as the vhdl integer type is only 32 bits wide. Removing unused constants.dsp/gc_pi_regulator: added enable input, fixed pipelining and strobe signals propagationgenrams: added g_implementation_hint RAM/FIFO attribute allowing to select the memory primitive used to implement the RAM.dsp/gc_soft_ramp_switch: added immediate kill/squelch output control signaldsp/gc_pi_regulator: fix error calculation signednessdsp/gc_iq_demodulator: sine should be 90 degrees after cosinedsp/gc_integer_divide: fix porting errors from uRVmodules/axi4_pkg: define default 512-bit full master output constantMerge branch '31-ciwbmasteraccessor-handle-multiple-requests' into 'proposed_master'hdl/sim: Protect CIWBMasterAccessor against multiple requestsconditional manifests for xilinx devicesbugfix: pcie_wb does not compile under modelsimradtol: improve secdec_32b package and tbradtol: add votersradtol: add Manifest.pyradtol: more fixesradtol: improve secded_32b testbenchradtol: improve secded_32b_pkgradtol/secded: add a testbench for secded_32b_pkgradtol: simplify secded_32b_pkgmodules/radtol: extract secded_32b_pkg from secded_ecc.vhdtb_secded_ecc.vhd: improve the testradtol: add a small testbench for secded_ecc.vhdsecded_ecc.vhd: add headersecded_ecc.vhd: minor cleanup (remove unused ports)Add radtol/secded_ecc.vhd from hydraconditional manifests for xilinx devicesaltera_worksaltera_works