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Created with Raphaël 2.2.01Jun31May151085228Apr18124331Mar151017Feb330Jan171613121120Dec191615142123Nov84310Oct7Sep110Aug83229Jul282520181628Jun2231May1222Mar1325Feb1711310Jan16Dec26Oct130Sep292823Aug929Jul11May615Apr11Mar17Feb161221Jan181512617Dec1611922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov29xwb_fine_pulse_gen: use dual-reset synchronizer, simplifies timing analysiswb_fine_pulse_gen: use correct clock domain reset for the FSMMerge branch '40-genram_pkg-disable-bound-checking-in-synthesis' into 'master'genram_pkg: disable bound check for RAM addresses in synthesizable codeMerge branch '39-gc_serial_dac-avoid-overwrite' into 'master'gc_serial_dac: ignore valid_i when we're not done with the current transferMerge branch '38-add-keep-attributes' into 'master'gc_sync[register]: keep attribute on the input clock pin [clk_i] for easy constraintsgc_reset_multi_aasd: add KEEP property on rst_chains so that we can easily constrain their timing in XDCMerge branch '37-gc_pulse_synchronizer2-use-async-reset' into 'master'gc_pulse_synchronizer2: use asynchronous reset for gc_edge_detectMerge branch '36-gc_sync-and-other-cdc-constraints-not-recognized-by-vivado' into 'master'tools: (hopefully) improved CDC constraints generation scripttools: (hopefully) improved CDC constraints generation scriptxwb_fine_pulse_gen: use dual-reset synchronizer, simplifies timing analysiswb_fine_pulse_gen: use correct clock domain reset for the FSMgenram_pkg: disable bound check for RAM addresses in synthesizable codegc_sync[register]: keep attribute on the input clock pin [clk_i] for easy constraintsgc_serial_dac: ignore valid_i when we're not done with the current transfergc_reset_multi_aasd: add KEEP property on rst_chains so that we can easily constrain their timing in XDCgc_pulse_synchronizer2: use asynchronous reset for gc_edge_detectmodules/genrams/generic/ replace log2 function bysowarzan-rfsowarzan-rfMerge branch 'mr-dsp' into 'master'testbench: fix gc_cordic testbenchsim: add sim_logger logging mechanismhdl: gc_cordic_top missing valid outSingle-file cordic fixing most of the quirks of the previous implementation with testbench.dsp: don't use generics (even statically evaluable) in case statement, it's not fully VHDL-compliant. Kudos to Tristan!Updated README.md with info about the DSP coresdsp: fix licensing, remove untested/unused/unlicensed codedsp/gc_cordic: move testbench to use Logger/UnitTest codedsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.dsp/gc_pi_regulator: synthesis fails when g_INTEGRATOR_BITS is bigger than 32 as the vhdl integer type is only 32 bits wide. Removing unused constants.dsp/gc_pi_regulator: added enable input, fixed pipelining and strobe signals propagationdsp/gc_soft_ramp_switch: added immediate kill/squelch output control signaldsp/gc_pi_regulator: fix error calculation signednessdsp/gc_iq_demodulator: sine should be 90 degrees after cosinedsp/gc_integer_divide: fix porting errors from uRVdsp: new IPs - integer divide/remainder unit and soft ramping switchdsp: rewrite gc_pi_regulator