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Created with Raphaël 2.2.023Aug929Jul11May615Apr11Mar17Feb161221Jan181512617Dec1611922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb26146Set fwnode to NULL after deallocationwb_fine_pulse_gen: fix incorrect reset signal for IDELAYCTRL for Ultrascale devicesMerge tag 'v1.1.2' into developMerge branch 'hotfix/v1.1.2'v1.1.2v1.1.2update changelogKernel 4.4: use fwnode for irq domainKernel 5.2 compatibility for i2c_new_deviceKernel 4.4: use fwnode for irq domainKernel 5.2 compatibility for i2c_new_devicewb_fine_pulse_gen: support for configurable pulse width. INTERFACE CHANGED.tom-rftom-rfgc_frequency_meter: DO NOT MERGE, temporary fix to make buggy vivado hierarchy solver happyvivado-2019.2vivado-2019.2wb_lm32: verilog header file must be *.vh otherwise Vivado 2019.2 is very unhappyAdd configurable reset state for sync/edge_detect IPsync_reset_statesync_reset_statewb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART likely not working. FIX BEFORE MERGING!pcie_altera: added pex10 and ftm10 instantiationpcie_altera: updated g_family stuffpcie_altera: addex pex10 and ftm10 componentaltera: updated PCIe HIP for arria10/ftm10altera: added tcl file for PCIe (ftm10)altera: Manifest.py -> added PCIe HIP for arria10/ftm10altera: updated PCIe HIP for arria10/pex10arria10gx_pex10_pcie_hip: updated gitignoreplatform/altera/networks: added arria10 networks to Manifest.pyaltera: added PCIe HIP for arria10/pex10altera: added arria10gx_pex10.tclPCIe: Manifest.py update (arria10/pex10)genrams/memory_loader_pkg: update condition to make it understandible for Libero/Synplifywishbone/wb_xc7_fw_update: add v2 without startupe2 (for wr2rf)wb_spi: add cheby file with registers definitionsim: add simple wb_spi SV driver for testbenchessim/if_wb_master: fix wb classic broken in commit cbc1c428: [sim] rewrite of the WB master interfacesim/if_wishbone_accessor: remove debug printouts added in commit 64f7e51added processing_system_pcie.bdpeter_210106_sp…peter_210106_spec7wb_uart: increase RX FIFO count register width to 16 bits to cater for large FIFOsRemove duplicate filename in common/Manifest.pywb_xc7_fw_update: keep STARTUP primitive outside the coretom-dec11tom-dec11README.md: mention wb_skidpad2Add wb_skidpad2.vhdMerge remote-tracking branch 'ohwr/svec-flash' into developsw: spi: Add check for Divider value