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Created with Raphaël 2.2.025Feb1711310Jan16Dec26Oct130Sep292823Aug929Jul11May615Apr11Mar17Feb161221Jan181512617Dec1611922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May212015dsp: testbench for gc_pipelined_fir_filterdsp/gc_iq_demodulator: remove decimation. Not used anywaydsp: added generic pipelined FIR filter coredsp/gc_cordic: make saturated math optional through a genericdsp: testbench for gc_cordicdsp/gc_cordic: fix translation errors introduced while porting the design from VEftm4: removed pcie core generated filesftm4: added pcie corewb_lm32: disable some features that choke ISE on Virtex5 targetsgenrams: KEEP attribute for FIFO resets to facilitate constrainingtom-afcz-v2tom-afcz-v2merging: solved conflictsgsi_master_get_…gsi_master_get_back_on_track_2022wishbone: added LM32 MCS and clock monitor cores to the manifestwishbone: added a clock frequency monitor core. LICENSING TO BE FIXEDwishbone: simple LM32-based microcontroller moduleinferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happymodules/common: added 'slow clock'/strobe pulse generator module. LICENSING TO BE FIXEDmodules/dsp: a collection of DSP modules ported from the CommonVisual library. Not yet tested. LICENSING TO BE FIXED!apply xilinx recommendation for clock domain crossing and sync resetesrf_v1.1.1esrf_v1.1.1Merge branch 'add_scoped_xdc' into 'proposed_master'Add scoped XDC constraints for CDC modulesMerge branch 'fix_issue_30' into 'proposed_master'Merge branch 'fix_issue_29' into 'proposed_master'Fix reset CDC issue in gc_sync_word_rdFix wb_ack_o violation in wb_simple_timerMerge branch 'release/v1.1.3'v1.1.3v1.1.3add CHANGELOGSet fwnode to NULL after deallocationwb_fine_pulse_gen: fix incorrect reset signal for IDELAYCTRL for Ultrascale devicesMerge tag 'v1.1.2' into developMerge branch 'hotfix/v1.1.2'v1.1.2v1.1.2update changelogKernel 4.4: use fwnode for irq domainKernel 5.2 compatibility for i2c_new_deviceKernel 4.4: use fwnode for irq domainKernel 5.2 compatibility for i2c_new_devicewb_fine_pulse_gen: support for configurable pulse width. INTERFACE CHANGED.tom-rftom-rfgc_frequency_meter: DO NOT MERGE, temporary fix to make buggy vivado hierarchy solver happyvivado-2019.2vivado-2019.2wb_lm32: verilog header file must be *.vh otherwise Vivado 2019.2 is very unhappyAdd configurable reset state for sync/edge_detect IPsync_reset_statesync_reset_statewb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART likely not working. FIX BEFORE MERGING!