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Created with Raphaël 2.2.028May2320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar28wb_pcie: converted arria2 ip to quartus 18.1gsi_master_a10gsi_master_a10common: added module that can count inc/dec pulses in different clk domainsgenrams: conditionally generate CDC synchronisers for async_fifos.common: reset cleanup for gc_frequency_meterMerge branch 'master' into proposed_mastercommon: added module that can count inc/dec pulses in different clk domainsFixed-latency-s…Fixed-latency-streamersgenrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written togenrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written tovirtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1greg-fifogreg-fifoREADME: document wishbone modules.gc_sync_word_wr.vhd: add comments.README: document rams and fifos (WIP)Manifest: fix axi package namemodules/common: add gc_comparator to packageMerge branch 'greg-axi' into proposed_mastermove axi-wb bridge to dedicated dir for AXImove axi4_pkg to dedicated directory for AXI modulesadding simple testbench for z7_axi_gpio_expanderaxi_gpio_expander: move to a separate directoryaxi_gpio_expander: bugfix to allow using a subset of bank0update ManifestsPL-PS AXI GPIO expander for both I/O banksPL-PS AXI GPIO expander (for Bank0 only)First version of AXI-GPIO expander for Zynq-7 (PL GPIO)genrams: rework g_show_ahead feature.README: complete with missing common designs (WIP).README.md: WIP - add more descriptions.WIP: more descriptions in README.mdAdd a top-level README (WIP)adding Axi4lite Master to WB Slave bridgegenrams: add initial values to rcb and wcb in async fifos to make simulators happierMerge branch 'dlamprid-dev' into proposed_mastertools: make mem_init_gen.py executableAdd clarifications for wishbone.wb_pcie: converted arria2 ip to quartus 18.1gsi_master_q18.1gsi_master_q18.1pcie_altera: improved arria 10 support for all deviceswb_pcie: updated arria10gx_e3p1_pcie_hip to current FPGApcie_altera: adapted arria10_pcie_hip and arria10gx_pcie_hip to quartus 18network: moved arria 10 fileswb_pcie: added pcie hip for gx generic