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Created with Raphaël 2.2.03Apr31Mar151017Feb330Jan171613121120Dec191615142123Nov84310Oct7Sep110Aug83229Jul282520181628Jun2231May1222Mar1325Feb1711310Jan16Dec26Oct130Sep292823Aug929Jul11May615Apr11Mar17Feb161221Jan181512617Dec1611922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov1713hdl: gc_cordic_top missing valid outtools: add version info from tag to gen_sourceid.pytools: add a couple of missing newlines to gen_sourceid.py outputtools: add comment to gen_sourceid.py explaining difference with gen_buildinfo.pywb_fine_pulse_gen: wip on testbenchwb_fine_pulse_gen: renaming of Cheby IP names to have a bit shorter register names in heeader filestypo in documentationwb_uart: testbench with regression cases against different combinations of FIFOs & VUART functionalitytom-proposed-ma…tom-proposed-master tom-uart-fixessim/axi/axi_test.sv addeed mising include declarationwb_uart: fixed broken VUART functionality with FIFOs enabledSingle-file cordic fixing most of the quirks of the previous implementation with testbench.wb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART likely not working. FIX BEFORE MERGING!wb_uart: increase RX FIFO count register width to 16 bits to cater for large FIFOswb_fine_pulse_gen: migrate to Cheby & merge eRTM14 and SIS83k variants of the FPGen Registerswb_fine_pulse_gen: implement output stage ready signaldsp: don't use generics (even statically evaluable) in case statement, it's not fully VHDL-compliant. Kudos to Tristan!xwb_axi4_bridge: fix issues with the AXI4 sidewrpc-v4.2-damc-…wrpc-v4.2-damc-fmc2zupMerge branch 'proposed_master' into 'master'Merge branch 'axi-test-suite' into 'proposed_master'Fixed common error in run.sh scripts for axi/Correct License added. Fixes done in order to solve the issue with axi4lite_axi4full_bridge assertion. sim_top_ps_gpio now not run foreverupdate testbench READMEcleanup testbench MakefileProperly ignore auto-generated files in AXI testbenchesIntroduce OSVVM dependency as submoduleAdded: Makefile to run automatically all the AXI tests and README file for explanationsAdding Testbench for AXI coresFinal update to README in AXI/ testskostas_devkostas_devREADME of AXI testbench changed. Also, now the user can change the simulation time before running the testUpdated README for AXI testbenchREADME changes in testnech directory and in AXI testbenchesmodules/wishbone/wb_spi/spi_top_wrap.sv added missing pin from spi_top modulesim: bring back Wishbone BFM headers to the root sim/ directory to avoid include search patch issueswishbone: declare clock/reset input explicitly as wiressim: fixed off-by-one error in test counting in Logger classsim: separate Manifest for AXI BFMsMerge branch 'tom-mr-new-wishbone-cores' into 'proposed_master'Merge branch 'tom-mr-genrams-improvements' into 'proposed_master'Merge branch 'tom-mr-new-wishbone-cores' into tom-proposed-masterMerge branch 'tom-mr-genrams-improvements' into tom-proposed-master