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Created with Raphaël 2.2.08Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18genrams/generic_shiftreg_fifo: force native SRL implementation on Xilinx devicesgenrams: removed dependency on Xilinx coregen, use native FIFO18/36 primitives on Virtex6common: improved RR arbiterserial_lcd: generic_dpram dual_clock generic matters now -- it was wronglm32: use generic_simple_dpram instead of custom memorygc_wfifo: eliminate custom memory; use generic_simple_dpram insteadaltera pcie: use generic_simple_dpram instead of custom memorygenrams: rewrote altera variants using altsyncramgenram: use init_file = "none" as an alternative to ""genram: add a "dont_care" option for g_addr_conflict_resolutiongenram: add a generic_simple_dpramgenrams: remove init_value generic optionlm32: off-by-one in memory initializationaltera pcie: tweak generated files to eliminate warningsaltera rams: use a default initial value of '0' to avoid hundreds of warningswb_slave_adapater: connect missing master output portsgc_wfifo: eliminate null range warnings when no sync chain usedgc_crc_gen: remove unused signalsaltera fifos: remove unused warningslm32: eliminate truncation warnings and make EBA_RESET a parameterlm32: prevent truncation warnings by explicitly selecting low bitslm32: one too many watch points => undefined warninglm32: remove unused signalslm32: add missing wires to silence warningsaltera pcie: do not reset PCIe when no slave bus is connectedserial_lcd: generic clock and row timingswb_pcie: include only on Alteraserial_lcd: WB interface to LCD displays with serial protocolaltera pcie: leave generated SDC constraints as a reference onlyaltera pcie: include in Manifest for hdlmakegc_reset: asynchronously clear the counterall: Regenerate Wishbone interfacescrossbar: eliminate lexically nested functionsAllow different clocks for slave+master interfacealtera/generic_dpram: Support Arria5wb_slave_adapter: rewrote using definition from the B.4 standard.generic_dpram: Should be read-first, as documented.pcie: Fix buffering bugsMake it possible to instantiate a PCIe-bridge without needing interrupt generation.Fully working reverse PCI bridge.