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Created with Raphaël 2.2.020Apr191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb26252119151413115Add a testbench for xwb_indirect.sim/vhdl: provide a simple vhdl package to generate WB transactions.README.md: mention wb_indirect.Add wishbone/wb_indirect.Remove use of intermediate variable in modules/genrams/Manifest.pyxwb_simple_uart: fixed typo causing a parse error...gc_sync_ffs: revert commit d2b71b651a191f96603385bce23d4112026a2b2d. It breaks the timestamper unit in wr_endpoint!wb_fine_pulse_gen: use double clock rate on Kintex7 Ultrascale, allowing for 1ns resolutiontom-fine-pulse-…tom-fine-pulse-gen-apr01genrams/cheby: also add cheby_pkg.vhdmodules/genrams: add new memory wrapper for cheby.wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)wb_fine_pulse_gen: extend WB registers with separate serdes reset and PLL lock indicatorxwb_fine_pulse_gen: fix PLL instantiation on Kintex Ultrascalewishbone: added Fine Pulse Generator modulecommon: added a simple non-WB SPI masteraxi4: add 512-bit data width AXI4-full record, fixed compilation issue in axi->wb bridgexwb_lm32: don't include wr_node/mockturtle profile in the VHDL wrapperwb_axi4lite_bridge: now conforms to AXI4 standardwb_simple_uart: allow preset baudrate register through a genericgc_enc_8b10b: added missing signals on process sensitivity list[hdl] add missing generic to generic_dpram in alterabtrain-v1.2btrain-v1.2wb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)wb_fine_pulse_gen: extend WB registers with separate serdes reset and PLL lock indicatorRemove unnecessary includes.cleanup_includescleanup_includes[hdl] add missing generic to generic_sync_fifo in genram_pkgxwb_fine_pulse_gen: fix PLL instantiation on Kintex Ultrascalewishbone: added Fine Pulse Generator modulefixed sel stuck at zero when readingpascal_axipascal_axi[hdl] avoid f_log2() circular dependencies in gc_extend_pulse[hdl] WIP to introduce a testbench for the WB SPI master.feature/wb_spi-…feature/wb_spi-simMerge tag 'v1.0.4' into proposed_masterMerge branch 'release/1.0.4'v1.0.4v1.0.4[bld] update changelog for new release.[bld] update changelog format.modules/genrams: more cleanup (for unused signals).xilinx/generic_dpram_sameclock: remove unused signals.sw:i2c: add support for kernel greater than 4.7Merge remote-tracking branch 'ohwr/proposed_master' into developMerge branch 'master' into developMerge remote-tracking branch 'ohwr/master'