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Created with Raphaël 2.2.08Jun29May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul2120191812Further relicensing to Solderpad v2 for all files used by masterFIPSolderpad license for WR PTP Coretools/sdb_desc_gen.tcl: replace non-ascii chars with '?' in all stringswb_simple_uart: added interrupt output pingc_frequency_meter: correctly scale output value according to the prescalertom-kintex7-ult…tom-kintex7-ultrascaletools: make SDB descriptor generator script less fragile wrt git commands. Also add header.hdl: Rename (again) wishbone dummy constants.hdl: add wb_remapper to wishbone_pkghdl: import f_pick functions from mockturtlehdl: introduce functions to convert characters and strings to std_logic_vectorsImport wb_remapper (from mock-turtle).hdl: fix component declaration for gc_i2c_slavewr-btrain-v1.1wr-btrain-v1.1hdl: rename wishbone dummy constants.hdl: introduce f_reduce_or to common packagehdl: add option to wb gpio to bypass input synchronizershdl: Eradicate INT from wishbone records and peripheral ports.Add f_to_std_logic function.gc_frequency_meter: make sure it works with no input clockmodified wb_pcie bridge has working white rabbithdl: minor fixes to wb crossbar and wb gpio to reduce synthesis and sim warningssim: update wishbone simulation modelstools: fix comments in sdb_desc_gen.tcltools: Introduce new Tcl script to automatically generate SDB meta informationRevert "increased address range of the cc_dummy_sdb_device"hdl: fix typo in common Manifestwb_i2c_bridge: Fix error in state-machineMerge branch 'masterFIP-v1.1.0' into proposed_masterxwb_lm32: expose all PC values for tracinggenrams: expose g_fail_if_init_file_not_found propertytom-masterfiptom-masterfipxwb_crossbar: optimized version with ~4x faster simulation timemodules/common: introduced gc_comparator and accompanying testbench[wishbone] bugfix: new g_sdb_name generic added to wrong entitiy inwrpc-v4.2wrpc-v4.2sdb_crossbar: generate more descriptive SDBno technical change, cleanup copyright holdersupdated manifestgc_sync_ffs: use unique sync chain register name so that a simple constraint can cover all false paths through clock synchronizerswipaxi4: add 512-bit data width AXI4-full record, fixed compilation issue in axi->wb bridgewishbone/wb_gpio_port: add simple testbenchwishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is not an exact multiple of 32. Closes #1532