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Created with Raphaël 2.2.02Sep30Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18added msi irq support for wishbonespi flash: support quad-lane 32MB+ chipsarria2: added direct clock network controlaltera pcie: force PCIe to a regional clock networkaltera: add direct control of clock networksdoc: compilation fixesaltera: add missing gc_shiftregMerge branch 'fix-arria5' into proposed_master (read notes!)wbgen2: arria5 does not support this read orderingproposed_master: fix previous merge master, wb_simple_pwm disappeared from Manifestproposed_master: fix previous merge master, wb_xilinx_fpga_loader was moved into platform/genrams/inferred_[a]sync_fifo: always handle write-to-full and read-from-empty situationswishbone/xwb_lm32: add user-defined reset vector as a generic parameterwishbone/wishbone_pkg: updated component for xwb_vicwishbone/wb_vic: vector table pre-initialization through a generic parameterwishbone/wb_lm32: drive unused ports in Xilinx primitive to 0 to ensure correct simulationsdb-crossbar: Fix record array size.sdb-crossbar: Remove extra generics, detects meta-info records internaly.sdb-crossbar: add support for meta-information records.arria2 pcie: use TCL to remove the bad generated SDC filealtera pcie: add arria5 + remove generate filesgc_sync_ffs: add constraints to prevent ISE from packing sync chain into shift regwb_simple_pwm: add generics for default PWM configurationset fake _almost empty_ and _almost full_ thresholds so that ISE 14.5 won't complainaltera pcie: use assigned vendor/device IDonewire: fix synthesis warningsaltera dcfifo: synchronize read resetaltera dpram: quell modelsim warningxwb_dma: convert custom array to generic_simple_dpramxwb_dma: convert variables into signalsxwb_streamer: reduce to a wrapper of xwb_dmamodules/common/Manifest.py: remove gc_dual_clock_ram, it's no more in the repogc_extend_pulse: save some resources, don't need to use fixed size 32-bit counteraltera pcie: fix a race condition in the bar switchoverremove gc_wfifo in favour of generic_async_fifoaltera: add flash interfacespi_flash: add enough parameters to work around buggy altera spi timingsserial_lcd + spi_flash: missing copyrightsspi_flash: memory-mapped flash memory (can program an Altera FPGA)move platform specific modules into conditional folders