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Created with Raphaël 2.2.01Apr28Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18irqm: correct out-of-date component definitiondoc: Update wb_i2c_bridge and add colored tables to other moduleswb_i2c_bridge: Make FSM watchdog setup more genericfix almost_full threshold for Virtex6 FIFO also in generic_async_fifoMerge branch 'master' into proposed_masterwb_uart: fix flow control on vuart rx pathMoved sync chain out of gc_glitch_filt, added gc_glitch_filt docMerge branch 'proposed_master' of ohwr.org:hdl-core-lib/general-cores into proposed_masteradded wb write function for slave interfaces to wishbone_pkginferred_async_fifo: Assigned full and almost full and empty outputs in all clock domainsfix almost_full threshold for Virtex6 FIFOswitch-optimization: generic to disable virtex6 fifo utilization countingmultiboot: Updated wbgen2 file for documentationi2c-bridge: Updated bridge and slave moduleswb_crossbar: allow extra SDB records at the end of the layoutmodules/wishbone: c_vuart_fifo_size exported as generic parameterwishbone_pkg: bugfix for f_sdb_create_arraygencores_pkg: added missing function declarations that were upsetting ISEUpdated some documentation filesSmall clean-up in gc_i2c_slave module and the instantiating wb_i2c_bridge moduleMade I2C slave and bridge work properlyUpdates in wb_xil_multiboot moduleFixed the FSM watchdog max value bugAdded gc_fsm_watchdog componentAdded new modules to libraryauto crossbar: appease modelsimMerge branch 'crossbar-improvements' into proposed_masterwishbone: sdb auto crossbar mapping supportsdb_crossbar: fix the meta-data ignore rule; disconnect the slave portcrossbar: allow slaves with address=0 and !mask=0 --> they are unreachablewishbone: add a timing cutteraltera pcie: add sdb record for MSI slave interfacemerged the proposed-master branchwb_irq: fix ack handling againgc_pulse_synchronizer2: double bandwidth and safer resetswb_irq: added global irq enable to irqm_corewb_irq: bug on ack line for irqm_core fixedMoved useful eca functionality to gencores_pkggenrams/inferred_sync_fifo.vhd: fix process sensitivity listwb_irq: appease modelsim