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Created with Raphaël 2.2.011Dec922Oct76130Sep181715149327Aug2619146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep18wb_xc7_fw_update: keep STARTUP primitive outside the coretom-dec11tom-dec11README.md: mention wb_skidpad2Add wb_skidpad2.vhdMerge remote-tracking branch 'ohwr/svec-flash' into developsw: spi: Add check for Divider valueadded processing_system_pcie.bdpeter_201007peter_201007renamed pci to pcie, moved to bd formatpascal_201006pascal_201006Added Pcie subsystemwb_uart: fix vuart, no show_ahead in fifowb_ds182x_readout: also report temperature status in temperature regtestbench: add a test for gc_ds182x_readoutwb_ds182x_readout: add the temp_ok status bitgc_ds182x_readout: extensive rewrite, add temp_ok_o port.Remove unnecessary includes.Merge branch 'greg-proposed_master' into 'proposed_master'Fixed UARTs too short delay between RX read and ACKgsi_master_get_…gsi_master_get_back_on_track_aug_2020Fixed bad wb_slave_adapter generics in crossbar sdb romsinstance_name attribute is not supported by Quartuswb_fine_pulse_gen: add missing rst_serdes inputwb_uart: add missing numeric_std packagewishbone: UART now supports configurable FIFOsMerge tag 'v1.1.1' into proposed_masterMerge tag 'v1.1.1' into developMerge branch 'release/v1.1.1' into masterv1.1.1v1.1.1update CHANGELOG for release 1.1.1sw:spi: fix update spi_message->actual_lengthFix response signalling in AXI4Lite-to-WB bridge wrapperFix BVALID signalling in AXI4Lite-to-WB bridge wrapperwb_simple_uart: allow preset baudrate register through a genericgc_enc_8b10b: added missing signals on process sensitivity listwb_fine_pulse_gen: simplify clock crossingsxwb_fine_pulse_gen: support for fine delay (ODELAYE3) on Kintex Ultrascalewb_fine_pulse_gen: use double clock rate on Kintex7 Ultrascale, allowing for 1ns resolutionwb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)wb_fine_pulse_gen: extend WB registers with separate serdes reset and PLL lock indicatorxwb_fine_pulse_gen: fix PLL instantiation on Kintex Ultrascalewishbone: added Fine Pulse Generator modulegc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed togethercommon: added a simple non-WB SPI masteraxi4: add 512-bit data width AXI4-full record, fixed compilation issue in axi->wb bridge