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Created with Raphaël 2.2.04Aug31Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18[switch-optimization]: wb_simple_pwm: add generic to set/reduce regs size[switch-optimization]: wb_i2c_master: adding support for multiple i2c interfaces[switch-optimization] wb_gpio_port optimized for gpio pins up to 32Renamed wb_xil_multiboot to xwb_xil_multibootAdded wb_xil_multiboot to wishbone_pkggc_frequency_meter.vhd: react on rising edge of gating signal (don't assume it's 1-cycle-wide)gencores_pkg: added f_onehot_encode()wb_spi_flash: fix off-by-one pipeline timing bugirq: included lm32 reset-vector genericirq: bug fix and some bullet proofing for irq masterwb_irq: fix bloody stupid mistake, overwrote file with wip garbage after test synthwb_irq: bugfix, irq_slave now always treats write enable correctlywishbone_pkg: Fix wishbone package dummy slave input constant.gencores_pkg: f_gen_dummy_vec belongs to genram_pkg. Declaring in both packages causes ambiguitysdb_address: add to the lm32 the generic for passingFix indentation and add comments.Add bicolor LED controller.Change dynamic glitch filter architecture.Add dynamic glitch filter (gc_dyn_glitch_filt).wishbone_pkg: Add sdb device record for xwb_spi component.spi flash: remove initialization and move erase to softwarewb_irq: include an SDB record for the master control interfacewb_irq: correct obvious typoMerge 'thedi-update-wb_i2c_bridge' into proposed_masterirqm: correct out-of-date component definitiondoc: Update wb_i2c_bridge and add colored tables to other moduleswb_i2c_bridge: Make FSM watchdog setup more genericfix almost_full threshold for Virtex6 FIFO also in generic_async_fifoMerge branch 'master' into proposed_masterwb_uart: fix flow control on vuart rx pathMoved sync chain out of gc_glitch_filt, added gc_glitch_filt docMerge branch 'proposed_master' of ohwr.org:hdl-core-lib/general-cores into proposed_masteradded wb write function for slave interfaces to wishbone_pkginferred_async_fifo: Assigned full and almost full and empty outputs in all clock domainsfix almost_full threshold for Virtex6 FIFOswitch-optimization: generic to disable virtex6 fifo utilization countingmultiboot: Updated wbgen2 file for documentationi2c-bridge: Updated bridge and slave moduleswb_crossbar: allow extra SDB records at the end of the layoutmodules/wishbone: c_vuart_fifo_size exported as generic parameter