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Created with Raphaël 2.2.03Feb26Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18minor improvements to reduce number of warnings generated by some of the coresxwb_lm32: expose all PC values for tracinghdl: added modification noticesdoc: added copy of original documentation for wb_spi and wb_onewire_masterwb_onewire_master: propagated CDR_N/O generics up the hierarchy; added assignments to (new) unspecified WB signalswb_onewire_master: added default values; typosgc_sync_register: added ASYNC_REG attribute for better timing analysis/simulation in Xilinx toolsgc_serial_dac: removed synchronous reset from sensitivity listshdl: added assignments to (new) unspecified WB signalshdl: added default values for determined start-up statecommon: introduced f_bool2int() and f_int2bool() conversion functionscommon/gc_i2c_slave: added option to allow automatic ACK of address byte without external user interventionsdb crossbar: #1401 fixed. Now properly handling sdb meta recordsMerge remote branch 'proposed_master' of ohwr.org:hdl-core-lib/general-cores into proposed_masterMerge remote-tracking branch 'origin/ML-Btrain-review-feedback' into proposed_masterMerge branch 'master' into proposed_masterMerge branch 'hotfix-sdb_commit_id_reversed_nibbles'sdb: fix nibble order in commit_id field of SDB synthesis record. Closes #1399.Merge branch 'hotfix-genram_xc6v_fix'wb: replaced xwb_register_link with more performant versiongeneric_shiftreg_fifo: assert almost_full_o one cycle in advancegenrams: fix problem with missing inferred fifos when target is xilinx virtex6. Solves #1396.added one-wire interface to DS1820/DS1822wb_lm32: add exception & bus errors support for the MockTurtle profilewb_lm32: add memory-mapped debug register access for Mockturtle/WRNode profilecommon: improved gc_moving_averagewb_lm32: enabled HW division for WR node profilewb_vic: IRQ retry option addedwishbone_pkg: added dummy device SDB recordgc_frequency_meter: use gc_pulse_synchronizer for external PPS pulse (in case the measured frequency is slower than the gating frequency)wb_lm32: 2x core clock logic can stay outside the LM32 corexwb_lm32: first version of WR node profileworking to add IRAM to LM32gc_async_signals_input_stage: fix generation of deglitched pulseThe added module is used in the SPEC-based WR-Btrain transmitter design.Added generation of sys_clk-synchronous global reset.arria2: updated pcie and clk networkspcie_wb: filter address bits unmapped by MSI crossbarpcie: remove obsolete SDB recordsdb rom: g_masters is not a good choice for invalid value (it can happen)