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Created with Raphaël 2.2.014Oct827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar28sw: add SPDX informationsw: add modules_install target on Makefilessw: align Makefilesimport htvic 1.3.0sw: include header filessw:i2c: unselecting is superfluoussw:drv:spi: fix pending testsw: improve build systemsw:drv: add SPI driver for spi-ocoressw:drv:i2c: fix directory namesw:drv: add I2C driver from LinuxClean-up non-ASCII characters and fix line feeds and terminations in all affected filespcie-wb: add configurable timeout after which the cycle line will be de-assertedpcie_wb_cyc_tim…pcie_wb_cyc_timeout[hdl] allow general-cores modules to work with hdlmake even when 'target' is not set[tools] update syndate field of buildinfo to include synthesis time as well[hdl][vic] do not mask RISR register. Closes #4[doc] fix address of VIC IVT_RAM. Closes #1direct-access: fix transaction count when ack or err coincides with stbpcie-wb-direct-…pcie-wb-direct-access[hdl] fix bug in gc_sync_word_rd with wrong signal used for loading the next inputgc_sync_word_*: use the same name to use the same constraints.Add gc_sync_word_rd core.[hdl] move assertion check from gc_sync_word_wr to gc_pulse_synchronizer[hdl] code cleanup of gc_frequency_meter[hdl] add g_SYNC_OUT option to gc_frequency meter.[hdl] re-work gc_sync_word_wr[hdl] gc_pulse_synchroniser2: add new output port ACKgen_buildinfo: also works in simulation mode.[tools] fix mem_init_gen to work with Python3add c_DUMMY_WB_SLAVE_D64_IN constantwb_vic: add fixed polarity; partial rewrite.Document wb_splitAdd wb_split core.Add gen_buildinfo.py file.f_string2svl: accept any bound for string parameter.wishbone_pkg: remove unused variable.Mention wb_metadata and add it to the Manifest.Add wb_metadata module.virtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1wr-switch-sw-v6.0wr-switch-sw-v6.0Move gc_ds182x_readout to a subdir, add README.Move gc_ds182x_readout.vhd to a subdirectory.