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Created with Raphaël 2.2.05Feb28Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun21109731May271143229Apr18wb_slave_adapter: rewrote using definition from the B.4 standard.generic_dpram: Should be read-first, as documented.pcie: Fix buffering bugsMake it possible to instantiate a PCIe-bridge without needing interrupt generation.Fully working reverse PCI bridge.Added interrupt generation as a wishbone interface.wishbone/wb_vic: added edge master interrupt emulationcommon/gc_pulse_synchronizer: trigger on edge, not levelbugfix: Reset counter was using wrong generic parameterCompile fix for Modelsim.Cleanup reset logic.Made errors reported by the crossbar prettier.Mathias' FIFO bug fix for when g_show_ahead is trueComponent definition was out-of-sync with entity as well.Added missing stall lineFixed memory initialization bug (Altera)wishbone/wb_xilinx_fpga_loader: added IDR registerwishbone/wb_xilinx_fpga_loader: startup the FPGA after write to CSR.EXITwishbone/wb_xilinx_fpga_loader: added boot trigger sequence and GPIO registerscommon/gc_extend_pulse: default output value to 0 to avoid simulation glitchesgenrams/generic_shiftreg_fifo: don't clear the FIFO contents on reset (this was causing inference of FFs instead of SRLs)Updated demonstration project files for revised PCIe core.Near-complete rewrite of the PCIe-WB4 bridge.Register reads did not match writes.Add a register to reset the LM32 over the PCIe bus.Include a demonstration Wishbone system, for quick-starting new developers.Disable a very poor Quartus "optimization"!Add a SDB record for the DMA controller.Added Manifest for PCIe bridge.There should be two register-register transfers in the same clock domainSilence a warning that the variable is not changed.Converted SDWB structures to new SDB format.Added a SDB register to BAR0None of our devices use the rty signal, but handle it for completeness.error flag endianess changedWe cannot stream reads.Never inspect Wishbone lines when CYC is low.Cannot register BAR twice; it will arrive too late.Regenerate with BAR1 64kB instead of 16MB.Fixed address decoding (width was wrong)