Merge requests · Projects / Platform-independent core collection · GitLab

Adding Testbench for AXI cores

!28 · created Jan 13, 2023 by Konstantinos Blantos proposed_master
- Merged
- 18
updated Jan 16, 2023
WIP: Kostas dev

!27 · created Jan 13, 2023 by Konstantinos Blantos proposed_master
- Closed
- 0
updated Jan 13, 2023
2 new WB cores

!26 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- Merged
- 4
updated Dec 16, 2022
Genrams improvements

!25 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- Merged
- 2
updated Dec 16, 2022
DSP core collection

!24 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- Closed
- 3
updated May 08, 2023
Minor updates to the AXI4 package

!23 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- 3
updated Dec 16, 2022
Rework of SystemVerilog shared simulation code

!22 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- 5
updated Dec 16, 2022
Resolve "tools: generate version information in gen_sourceid.py"

!21 · created Dec 15, 2022 by Dimitris Lampridis
- Merged
- 2
updated Dec 15, 2022
Wb axi4lite bridge fix

!20 · created Oct 09, 2022 by Peter Jansweijer
- Closed
- 1
updated Oct 10, 2022
hdl/sim: Protect CIWBMasterAccessor against multiple requests

!19 · created Jul 14, 2022 by Dimitris Lampridis proposed_master
- Merged
- 17
updated Jul 18, 2022
Making libs more versatile for Altera/Modelsim

!18 · created Jun 27, 2022 by David Belohrad proposed_master
- Closed
- 1
updated Jun 28, 2022
Fixed an issue where the "RESPONSE_READ" was skipped.

!17 · created May 13, 2022 by Pascal Bos proposed_master
bug
- 0
Add scoped XDC constraints for CDC modules

!16 · created Sep 30, 2021 by Adrian Byszuk proposed_master
- Merged
- 1
updated Oct 01, 2021
Fix reset CDC issue in gc_sync_word_rd

!15 · created Sep 28, 2021 by Adrian Byszuk proposed_master
- Merged
- 1
updated Sep 29, 2021
Fix wb_ack_o violation in wb_simple_timer

!14 · created Sep 28, 2021 by Adrian Byszuk proposed_master
- Merged
- 1
updated Sep 29, 2021
Condition check for Divider value

!13 · created Oct 22, 2020 by Mamta Shukla
- Closed
- 1
updated Oct 22, 2020
Merge current master into current GSI development branch

!12 · created Oct 12, 2020 by A. Hahn gsi_master_get_back_on_track_aug_2020
- Closed
- 0
updated Oct 12, 2020
Fixes to the latest proposed_master merge

!11 · created Sep 15, 2020 by Grzegorz Daniluk proposed_master
- Merged
- 0
updated Sep 17, 2020
[sw][driver][spi]: Update actual_length to fix I/O error

!10 · created Sep 11, 2020 by Mamta Shukla
- Closed
- 1
updated Sep 14, 2020
AFCZ-related fixes (SPI, etc)

!9 · created Aug 27, 2020 by Tomasz Wlostowski proposed_master
- Closed
- 1
updated Sep 09, 2020

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