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hdl/sim: Protect CIWBMasterAccessor against multiple requests

When performing reads/writes from multiple threads, CIWBMasterAccessor does not provide any protection, leading to data from one request being delivered to another.

By replacing the data queues with SV mailboxes, we ensure that only one thread can access the mailbox at any given time. Furthermore, we make sure that if the request mailbox is in use, the other thread(s) must wait for a clock cycle. As a result only one request will be submitted at every cycle (at maximum, it could be less). Once a thread has submitted a request, it will immediately claim the result mailbox, preventing subsequent requests from other threads from "stealing" the result.

Closes #31 (closed)

Edited by Dimitris Lampridis

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