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Rework of SystemVerilog shared simulation code

Tomasz Wlostowski requested to merge tom-mr-sv-sim-rework into proposed_master
  • Rework simdrv_defs into a SV package + header with common definitions.
  • Use SV queues instead of dynamic arrays in the APIs (as they resemble C++'s std::vector a bit more, hence are more convenient to use)
  • Added AXI4 BFMs from the PULP project library
  • Added a bunch of simulation drivers (for the VUART & LM32 MCS cores)
  • Added a trivial unit test/logging "framework" (logger.svh)
  • Updated license headers
  • Updated build scripts for testbenches using the SV models.

Note these changes will likely break your legacy testbenches, here's how to fix the most common issues:

  • If your code uses CBusAccessor::readm/writem, change the addr/data parameters to use SV queues (or u64_vector_t types) instead of dynamic arrays.
Edited by Tomasz Wlostowski

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