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Programming languages used in this repository

Measured in bytes of code. Excludes generated and vendored code.

PercentageUsed programming language01020304050VHDLVerilogStataCSystemVerilog

Commit statistics for 4f414ececa8286f49bc6324425a00b9561884375 Apr 18 - Oct 14

Excluding merge commits. Limited to 2,000 commits.
Switch branch/tag
  • 45-addition-of-a-register-in-wb_uart-to-show-the-endianess
  • 46-demo_vunit_ghdl_testbench
  • 47-revert-version-of-wb_uart
  • 51-inferred_async_fifo_dual_reset-spurious-pulse-on-almost_full_int-after-reset
  • 52-possible_fix_in_wb_uart_rx_fifo
  • 56-axi4_pkg-incorrect-width
  • Fixed-latency-streamers
  • ML-new_wrs-4_resource_eval
  • altera_works
  • btrain-v1.2
  • cleanup_includes
  • cordic_changes
  • esrf_v1.1.1
  • feature/i2c/modernise
  • feature/wb_spi-sim
  • for-simulated-hw
  • greg-fifo
  • gsi_fallout_release
  • gsi_fallout_release_quartus_23_1_1
  • gsi_master
  • wr-switch-sw-v8.0
  • wr-switch-sw-v7.0
  • wr-switch-sw-v6.0
  • v1.1.4
  • v1.1.3
  • v1.1.2
  • v1.1.1
  • v1.1.0
  • spec7_v4.2
  • btrain-v1.2
  • v1.0.2
  • v1.0.1
  • v1.0.4
  • v1.0.3
  • v1.0.0
  • btrain-v2.5
  • wr-btrain-v1.1
  • masterFIP_v1.1.0
  • wrpc-v4.2
  • wrpc-v4.1
40 results
  • Total: 778 commits
  • Average per day: 0.3 commits
  • Authors: 22

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Commits per day hour (UTC)

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