When trying to compile for nanoXplore synthesis fails, complaining
about those signals -- although they're unused.

Maciej Lipinski authored 5 years ago and Dimitris Lampridis committed 5 years ago

This is needed for fixed-latency streamers. Module was written by Tom,
he added it to wr-cores whereas it belongs here, I've moved it.

This is beneficial because the gc_sync_ffs has a Xilinx "keep" attribute, which prevents the tools
from trimming out unused logic, even when the user has set the relevant generics to "FALSE".

genrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written to

genrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written to

The previous implementation was introducing latches to the GN4124 core under Xilinx ISE.

Tested and verified to work with the following SPEC-based reference designs:
 - WR
 - MT
 - WRTD